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Date: Tue, 13 May 2014 10:45:24 +0200
Message-ID: <CACRpkdZ+OG0FXkgnkdiyhRobSvo+9=ouXc6qes_UCGhitFhTXQ@mail.gmail.com>
Subject: Re: [PATCH 1/7] ARM: dts: socfpga: add gpio pieces
From: Linus Walleij <linus.walleij@linaro.org>
To: Olof Johansson <olof@lixom.net>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
        Alan Tull <atull@altera.com>, Alexandre Courbot <gnurou@gmail.com>,
        "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Dinh Nguyen <dinguyen@altera.com>,
        Alan Tull <delicious.quinoa@gmail.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
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On Tue, May 6, 2014 at 12:02 AM, Olof Johansson <olof@lixom.net> wrote:

> ... or is there some underlying reason for having the two-layer
> approach that isn't obvious from this device tree?

There is, as explained by Alan. One coherent memory range with
several individual ports.

Yours,
Linus Walleij