From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2DC4C00A89 for ; Thu, 5 Nov 2020 07:11:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38A7720936 for ; Thu, 5 Nov 2020 07:11:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZQT1WmbX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727098AbgKEHL5 (ORCPT ); Thu, 5 Nov 2020 02:11:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725861AbgKEHL4 (ORCPT ); Thu, 5 Nov 2020 02:11:56 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30EB5C0613CF for ; Wed, 4 Nov 2020 23:11:54 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id p15so440553ljj.8 for ; Wed, 04 Nov 2020 23:11:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WNBLtQhx0lIFZsfU2449a/+PzoBFm8WIuwQ69CU7rMc=; b=ZQT1WmbXOd3h+w+nHhJ1Vt1wtFDtE/mjJXAk3jAt2FGb0tLGDkEZJA9vr0UOxMJish 8ii1IbOpAn0cbLZ9pCu4GcErW25ODUZam+oFxBZJvQ0UxoSB69UopiAj4o8l5CrAlTsY 2gI+iNB8RUd8Pm3qH9WXxldgchh2IC3D/8tc5FWen4NyKWHmXWVP7ClT29/K8YeMoUbF YRear4W1ywXxsn8x2uJCzjPu5UcrZ7P26pW+AR9wohFxpS1uy/M16oooCzBNDITBJRNg AgJtZN3qVpdKC5FCW3i6N1ag2HjSXsjUqwcgUnWsoim4ZpYYvORCcaDMntQQjr4eV4Yt b11A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WNBLtQhx0lIFZsfU2449a/+PzoBFm8WIuwQ69CU7rMc=; b=kLH4wz2R/xFKHIQscdzShBdWY6ZXZQJ5IRwwZFxOGlYzMupOSMvzw38RlOBc8CwCUY E88Whc59sBMUXMgFPfIGH7F/lAi0erCB2riQLKrSbo0hOZEeTCgSaiYfTQ0HUsQIUnrX LQ6+zMLq5D7HoFUTjDwioPB1uDwz1FDtPD0WosxJioG0O4qVgbGpiKLVAI3bJmJC1w66 EgkD7oAZ+3RgPMkT+MWnoG7jmvuJqM4hLi8AtujV4y0QE3+99ykG2jGqNmCAHEhg9s/8 82Fq6NixZ/T0r12V/QeYQdBtlQkQK5VW+JkaNWyMajIpwfHdZrr47mbi1OYBZx7lxF7E BydA== X-Gm-Message-State: AOAM532byRU/BBYrqekdq+SRUmat+KhQYQDUQR39mb2feLhpaDr3eiph xrgEejCmu7sQdj9Kb/pZGxb2Fjr/VJZROj7aW46UHg== X-Google-Smtp-Source: ABdhPJwYr72s3R4wIoyLlWiPnehmVLojv0mw4p7dpc7yNaYK2lfaYqyj0E3H340JMs3ERbhuf3MCk8LH9YBkbX7UVaQ= X-Received: by 2002:a05:651c:1050:: with SMTP id x16mr388615ljm.100.1604560312669; Wed, 04 Nov 2020 23:11:52 -0800 (PST) MIME-Version: 1.0 References: <20201030053153.5319-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20201030053153.5319-4-vadivel.muruganx.ramuthevar@linux.intel.com> In-Reply-To: <20201030053153.5319-4-vadivel.muruganx.ramuthevar@linux.intel.com> From: Linus Walleij Date: Thu, 5 Nov 2020 08:11:41 +0100 Message-ID: Subject: Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC To: "Ramuthevar,Vadivel MuruganX" Cc: Mark Brown , Vignesh R , Tudor Ambarus , "linux-kernel@vger.kernel.org" , linux-spi , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , Simon Goldschmidt , Dinh Nguyen , Richard Weinberger , cheol.yong.kim@intel.com, qi-ming.wu@intel.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX wrote: > + ddata = of_device_get_match_data(dev); > + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) { > + if (of_property_read_u32(np, "num-chipselect", The standard SPI bindings in spi-controller.yaml already has a binding for this "num-cs" so please use that. It is also what your device tree binding is referencing, so if you were using "num-chipselect" the YAML check should give a warning? Yours, Linus Walleij