From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756641AbcIGThY (ORCPT ); Wed, 7 Sep 2016 15:37:24 -0400 Received: from mail-oi0-f47.google.com ([209.85.218.47]:36426 "EHLO mail-oi0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753541AbcIGThU (ORCPT ); Wed, 7 Sep 2016 15:37:20 -0400 MIME-Version: 1.0 In-Reply-To: <20160907145400.27192-4-maxime.ripard@free-electrons.com> References: <20160907145400.27192-1-maxime.ripard@free-electrons.com> <20160907145400.27192-4-maxime.ripard@free-electrons.com> From: Linus Walleij Date: Wed, 7 Sep 2016 21:37:19 +0200 Message-ID: Subject: Re: [PATCH v2 3/4] ARM: dts: Add NextThing GR8 dtsi To: Maxime Ripard , Laurent Pinchart Cc: Chen-Yu Tsai , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , Mylene Josserand , Thomas Petazzoni , Alexander Kaplan Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id u87JbUXC018511 On Wed, Sep 7, 2016 at 4:53 PM, Maxime Ripard wrote: > From: Mylène Josserand > > The GR8 is an SoC made by Nextthing loosely based on the sun5i family. > > Since it's not clear yet what we can factor out and merge with the A10s and > A13 support, let's keep it out of the sun5i.dtsi include tree. We will > figure out what can be shared when things settle down. > > Signed-off-by: Mylène Josserand > Signed-off-by: Maxime Ripard Acked-by: Linus Walleij I was just thinking: > + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PB0", "PB1"; > + allwinner,function = "i2c0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; It would be *NICE* if the sunxi driver would start to support the new standard bindings for this stuff, see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt So you could just use pins, function and the drive-strength and bias-disable in this case. Since I know the AllWinner support is a community project I have much higher tolerance with this legacy binding sticking around for the new generation of SoCs but still, if you find time. I mean it like supporting these in *addition* to the custom ones, so there can be a smooth phase-over. Check for example Laurent's commit for SH-PFC: commit 16ccaf5bb5a52372bfebd3dfbb79dd810ad49c09 "pinctrl: sh-pfc: Accept standard function, pins and groups properties" It's awesome, and since, they have improved the looks of Renesas DTS files a lot. It could look a bit like this nice thing from lpc4337-ciaa.dts: &pinctrl { enet_rmii_pins: enet-rmii-pins { enet_rmii_rxd_cfg { pins = "p1_15", "p0_0"; function = "enet"; slew-rate = <1>; bias-disable; input-enable; input-schmitt-disable; }; enet_rmii_txd_cfg { pins = "p1_18", "p1_20"; function = "enet"; slew-rate = <1>; bias-disable; input-enable; input-schmitt-disable; }; (etc) Yours, Linus Walleij