This is a little series to add a compatible string for the Sigmastar SSD201 and SSD202D to the msc313 gpio driver, add the specific offsets for the pins on these chips, and then a bunch of DT wiring stuff so that the LEDs on the M5 stack unitv2 work and it can control the power switch for the USB connected. Daniel Palmer (10): dt-bindings: gpio: msc313: Add compatible for ssd20xd dt-bindings: gpio: msc313: Add offsets for ssd20xd gpio: msc313: Code clean ups gpio: msc313: Add support for SSD201 and SSD202D ARM: dts: mstar: Set gpio compatible for ssd20xd ARM: dts: mstar: unitv2: Wire up LEDs ARM: dts: mstar: unitv2: Add core regulator ARM: dts: mstar: unitv2: Add io regulator ARM: dts: mstar: unitv2: Add DRAM regulator ARM: dts: mstar: unitv2: Add wifi switch .../bindings/gpio/mstar,msc313-gpio.yaml | 4 +- .../dts/mstar-infinity2m-ssd202d-unitv2.dts | 46 +++ .../boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 + drivers/gpio/gpio-msc313.c | 266 +++++++++++++++++- include/dt-bindings/gpio/msc313-gpio.h | 71 +++++ 5 files changed, 387 insertions(+), 5 deletions(-) -- 2.32.0
Add a compatible string for "ssd20xd" for the SigmaStar SSD201 and SSD202D chips. These chips are the same die with different memory bonded so they don't need their own strings. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml index fe1e1c63ffe3..18fe90387b87 100644 --- a/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml @@ -14,7 +14,9 @@ properties: pattern: "^gpio@[0-9a-f]+$" compatible: - const: mstar,msc313-gpio + enum: + - mstar,msc313-gpio + - sstar,ssd20xd-gpio reg: maxItems: 1 -- 2.32.0
Add the gpio offsets for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- include/dt-bindings/gpio/msc313-gpio.h | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h index 2dd56683d3c1..5458c6580a02 100644 --- a/include/dt-bindings/gpio/msc313-gpio.h +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -50,4 +50,75 @@ #define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) #define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) +/* SSD20x */ +#define SSD20XD_GPIO_FUART 0 +#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0) +#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1) +#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2) +#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3) + +#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1) +#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0) +#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1) +#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2) +#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3) +#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4) +#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5) + +#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1) +#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0) +#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1) + +#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1) +#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0) +#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1) + +#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1) +#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0) +#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1) +#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2) +#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3) +#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4) +#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5) +#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6) +#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7) +#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8) +#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9) +#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10) +#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11) +#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12) +#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13) +#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14) +#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15) +#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16) +#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17) +#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18) +#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19) +#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20) +#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21) +#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22) +#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23) +#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24) +#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25) +#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26) +#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27) + +#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1) +#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0) +#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1) +#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2) +#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3) +#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4) +#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5) +#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6) +#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7) +#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8) +#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9) +#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10) +#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11) +#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12) +#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13) +#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14) +#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15) + #endif /* _DT_BINDINGS_MSC313_GPIO_H */ -- 2.32.0
- Remove the unneeded assignment of ret before returning it. - Remove an unneeded blank line Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- drivers/gpio/gpio-msc313.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-msc313.c b/drivers/gpio/gpio-msc313.c index da31a5ff7a2b..a894bafbd4c3 100644 --- a/drivers/gpio/gpio-msc313.c +++ b/drivers/gpio/gpio-msc313.c @@ -344,7 +344,6 @@ static int msc313_gpio_probe(struct platform_device *pdev) struct irq_domain *parent_domain; struct device_node *parent_node; struct device *dev = &pdev->dev; - int ret; match_data = of_device_get_match_data(dev); if (!match_data) @@ -399,8 +398,7 @@ static int msc313_gpio_probe(struct platform_device *pdev) gpioirqchip->handler = handle_bad_irq; gpioirqchip->default_type = IRQ_TYPE_NONE; - ret = devm_gpiochip_add_data(dev, gpiochip, gpio); - return ret; + return devm_gpiochip_add_data(dev, gpiochip, gpio); } static int msc313_gpio_remove(struct platform_device *pdev) @@ -456,5 +454,4 @@ static struct platform_driver msc313_gpio_driver = { .probe = msc313_gpio_probe, .remove = msc313_gpio_remove, }; - builtin_platform_driver(msc313_gpio_driver); -- 2.32.0
This adds GPIO support for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- drivers/gpio/gpio-msc313.c | 261 +++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) diff --git a/drivers/gpio/gpio-msc313.c b/drivers/gpio/gpio-msc313.c index a894bafbd4c3..b2c90bdd39d0 100644 --- a/drivers/gpio/gpio-msc313.c +++ b/drivers/gpio/gpio-msc313.c @@ -221,6 +221,263 @@ static const unsigned int msc313_offsets[] = { }; MSC313_GPIO_CHIPDATA(msc313); + +/* + * Unlike the msc313(e) the ssd20xd have a bunch of pins + * that are actually called gpio probably because they + * have no dedicated function. + */ +#define SSD20XD_PINNAME_GPIO0 "gpio0" +#define SSD20XD_PINNAME_GPIO1 "gpio1" +#define SSD20XD_PINNAME_GPIO2 "gpio2" +#define SSD20XD_PINNAME_GPIO3 "gpio3" +#define SSD20XD_PINNAME_GPIO4 "gpio4" +#define SSD20XD_PINNAME_GPIO5 "gpio5" +#define SSD20XD_PINNAME_GPIO6 "gpio6" +#define SSD20XD_PINNAME_GPIO7 "gpio7" +#define SSD20XD_PINNAME_GPIO10 "gpio10" +#define SSD20XD_PINNAME_GPIO11 "gpio11" +#define SSD20XD_PINNAME_GPIO12 "gpio12" +#define SSD20XD_PINNAME_GPIO13 "gpio13" +#define SSD20XD_PINNAME_GPIO14 "gpio14" +#define SSD20XD_PINNAME_GPIO85 "gpio85" +#define SSD20XD_PINNAME_GPIO86 "gpio86" +#define SSD20XD_PINNAME_GPIO90 "gpio90" + +#define SSD20XD_GPIO_NAMES SSD20XD_PINNAME_GPIO0, \ + SSD20XD_PINNAME_GPIO1, \ + SSD20XD_PINNAME_GPIO2, \ + SSD20XD_PINNAME_GPIO3, \ + SSD20XD_PINNAME_GPIO4, \ + SSD20XD_PINNAME_GPIO5, \ + SSD20XD_PINNAME_GPIO6, \ + SSD20XD_PINNAME_GPIO7, \ + SSD20XD_PINNAME_GPIO10, \ + SSD20XD_PINNAME_GPIO11, \ + SSD20XD_PINNAME_GPIO12, \ + SSD20XD_PINNAME_GPIO13, \ + SSD20XD_PINNAME_GPIO14, \ + SSD20XD_PINNAME_GPIO85, \ + SSD20XD_PINNAME_GPIO86, \ + SSD20XD_PINNAME_GPIO90 + +#define SSD20XD_GPIO_OFF_GPIO0 0x0 +#define SSD20XD_GPIO_OFF_GPIO1 0x4 +#define SSD20XD_GPIO_OFF_GPIO2 0x8 +#define SSD20XD_GPIO_OFF_GPIO3 0xc +#define SSD20XD_GPIO_OFF_GPIO4 0x10 +#define SSD20XD_GPIO_OFF_GPIO5 0x14 +#define SSD20XD_GPIO_OFF_GPIO6 0x18 +#define SSD20XD_GPIO_OFF_GPIO7 0x1c +#define SSD20XD_GPIO_OFF_GPIO10 0x28 +#define SSD20XD_GPIO_OFF_GPIO11 0x2c +#define SSD20XD_GPIO_OFF_GPIO12 0x30 +#define SSD20XD_GPIO_OFF_GPIO13 0x34 +#define SSD20XD_GPIO_OFF_GPIO14 0x38 +#define SSD20XD_GPIO_OFF_GPIO85 0x100 +#define SSD20XD_GPIO_OFF_GPIO86 0x104 +#define SSD20XD_GPIO_OFF_GPIO90 0x114 + +#define SSD20XD_GPIO_OFFSETS SSD20XD_GPIO_OFF_GPIO0, \ + SSD20XD_GPIO_OFF_GPIO1, \ + SSD20XD_GPIO_OFF_GPIO2, \ + SSD20XD_GPIO_OFF_GPIO3, \ + SSD20XD_GPIO_OFF_GPIO4, \ + SSD20XD_GPIO_OFF_GPIO5, \ + SSD20XD_GPIO_OFF_GPIO6, \ + SSD20XD_GPIO_OFF_GPIO7, \ + SSD20XD_GPIO_OFF_GPIO10, \ + SSD20XD_GPIO_OFF_GPIO11, \ + SSD20XD_GPIO_OFF_GPIO12, \ + SSD20XD_GPIO_OFF_GPIO13, \ + SSD20XD_GPIO_OFF_GPIO14, \ + SSD20XD_GPIO_OFF_GPIO85, \ + SSD20XD_GPIO_OFF_GPIO86, \ + SSD20XD_GPIO_OFF_GPIO90 + +/* "ttl" pins lcd interface pins */ +#define SSD20XD_PINNAME_TTL0 "ttl0" +#define SSD20XD_PINNAME_TTL1 "ttl1" +#define SSD20XD_PINNAME_TTL2 "ttl2" +#define SSD20XD_PINNAME_TTL3 "ttl3" +#define SSD20XD_PINNAME_TTL4 "ttl4" +#define SSD20XD_PINNAME_TTL5 "ttl5" +#define SSD20XD_PINNAME_TTL6 "ttl6" +#define SSD20XD_PINNAME_TTL7 "ttl7" +#define SSD20XD_PINNAME_TTL8 "ttl8" +#define SSD20XD_PINNAME_TTL9 "ttl9" +#define SSD20XD_PINNAME_TTL10 "ttl10" +#define SSD20XD_PINNAME_TTL11 "ttl11" +#define SSD20XD_PINNAME_TTL12 "ttl12" +#define SSD20XD_PINNAME_TTL13 "ttl13" +#define SSD20XD_PINNAME_TTL14 "ttl14" +#define SSD20XD_PINNAME_TTL15 "ttl15" +#define SSD20XD_PINNAME_TTL16 "ttl16" +#define SSD20XD_PINNAME_TTL17 "ttl17" +#define SSD20XD_PINNAME_TTL18 "ttl18" +#define SSD20XD_PINNAME_TTL19 "ttl19" +#define SSD20XD_PINNAME_TTL20 "ttl20" +#define SSD20XD_PINNAME_TTL21 "ttl21" +#define SSD20XD_PINNAME_TTL22 "ttl22" +#define SSD20XD_PINNAME_TTL23 "ttl23" +#define SSD20XD_PINNAME_TTL24 "ttl24" +#define SSD20XD_PINNAME_TTL25 "ttl25" +#define SSD20XD_PINNAME_TTL26 "ttl26" +#define SSD20XD_PINNAME_TTL27 "ttl27" + +#define SSD20XD_TTL_PINNAMES SSD20XD_PINNAME_TTL0, \ + SSD20XD_PINNAME_TTL1, \ + SSD20XD_PINNAME_TTL2, \ + SSD20XD_PINNAME_TTL3, \ + SSD20XD_PINNAME_TTL4, \ + SSD20XD_PINNAME_TTL5, \ + SSD20XD_PINNAME_TTL6, \ + SSD20XD_PINNAME_TTL7, \ + SSD20XD_PINNAME_TTL8, \ + SSD20XD_PINNAME_TTL9, \ + SSD20XD_PINNAME_TTL10, \ + SSD20XD_PINNAME_TTL11, \ + SSD20XD_PINNAME_TTL12, \ + SSD20XD_PINNAME_TTL13, \ + SSD20XD_PINNAME_TTL14, \ + SSD20XD_PINNAME_TTL15, \ + SSD20XD_PINNAME_TTL16, \ + SSD20XD_PINNAME_TTL17, \ + SSD20XD_PINNAME_TTL18, \ + SSD20XD_PINNAME_TTL19, \ + SSD20XD_PINNAME_TTL20, \ + SSD20XD_PINNAME_TTL21, \ + SSD20XD_PINNAME_TTL22, \ + SSD20XD_PINNAME_TTL23, \ + SSD20XD_PINNAME_TTL24, \ + SSD20XD_PINNAME_TTL25, \ + SSD20XD_PINNAME_TTL26, \ + SSD20XD_PINNAME_TTL27 + +#define SSD20XD_TTL_OFFSET_TTL0 0x80 +#define SSD20XD_TTL_OFFSET_TTL1 0x84 +#define SSD20XD_TTL_OFFSET_TTL2 0x88 +#define SSD20XD_TTL_OFFSET_TTL3 0x8c +#define SSD20XD_TTL_OFFSET_TTL4 0x90 +#define SSD20XD_TTL_OFFSET_TTL5 0x94 +#define SSD20XD_TTL_OFFSET_TTL6 0x98 +#define SSD20XD_TTL_OFFSET_TTL7 0x9c +#define SSD20XD_TTL_OFFSET_TTL8 0xa0 +#define SSD20XD_TTL_OFFSET_TTL9 0xa4 +#define SSD20XD_TTL_OFFSET_TTL10 0xa8 +#define SSD20XD_TTL_OFFSET_TTL11 0xac +#define SSD20XD_TTL_OFFSET_TTL12 0xb0 +#define SSD20XD_TTL_OFFSET_TTL13 0xb4 +#define SSD20XD_TTL_OFFSET_TTL14 0xb8 +#define SSD20XD_TTL_OFFSET_TTL15 0xbc +#define SSD20XD_TTL_OFFSET_TTL16 0xc0 +#define SSD20XD_TTL_OFFSET_TTL17 0xc4 +#define SSD20XD_TTL_OFFSET_TTL18 0xc8 +#define SSD20XD_TTL_OFFSET_TTL19 0xcc +#define SSD20XD_TTL_OFFSET_TTL20 0xd0 +#define SSD20XD_TTL_OFFSET_TTL21 0xd4 +#define SSD20XD_TTL_OFFSET_TTL22 0xd8 +#define SSD20XD_TTL_OFFSET_TTL23 0xdc +#define SSD20XD_TTL_OFFSET_TTL24 0xe0 +#define SSD20XD_TTL_OFFSET_TTL25 0xe4 +#define SSD20XD_TTL_OFFSET_TTL26 0xe8 +#define SSD20XD_TTL_OFFSET_TTL27 0xec + +#define SSD20XD_TTL_OFFSETS SSD20XD_TTL_OFFSET_TTL0, \ + SSD20XD_TTL_OFFSET_TTL1, \ + SSD20XD_TTL_OFFSET_TTL2, \ + SSD20XD_TTL_OFFSET_TTL3, \ + SSD20XD_TTL_OFFSET_TTL4, \ + SSD20XD_TTL_OFFSET_TTL5, \ + SSD20XD_TTL_OFFSET_TTL6, \ + SSD20XD_TTL_OFFSET_TTL7, \ + SSD20XD_TTL_OFFSET_TTL8, \ + SSD20XD_TTL_OFFSET_TTL9, \ + SSD20XD_TTL_OFFSET_TTL10, \ + SSD20XD_TTL_OFFSET_TTL11, \ + SSD20XD_TTL_OFFSET_TTL12, \ + SSD20XD_TTL_OFFSET_TTL13, \ + SSD20XD_TTL_OFFSET_TTL14, \ + SSD20XD_TTL_OFFSET_TTL15, \ + SSD20XD_TTL_OFFSET_TTL16, \ + SSD20XD_TTL_OFFSET_TTL17, \ + SSD20XD_TTL_OFFSET_TTL18, \ + SSD20XD_TTL_OFFSET_TTL19, \ + SSD20XD_TTL_OFFSET_TTL20, \ + SSD20XD_TTL_OFFSET_TTL21, \ + SSD20XD_TTL_OFFSET_TTL22, \ + SSD20XD_TTL_OFFSET_TTL23, \ + SSD20XD_TTL_OFFSET_TTL24, \ + SSD20XD_TTL_OFFSET_TTL25, \ + SSD20XD_TTL_OFFSET_TTL26, \ + SSD20XD_TTL_OFFSET_TTL27 + +/* On the ssd20xd the two normal uarts have dedicated pins */ +#define SSD20XD_PINNAME_UART0_RX "uart0_rx" +#define SSD20XD_PINNAME_UART0_TX "uart0_tx" + +#define SSD20XD_UART0_NAMES \ + SSD20XD_PINNAME_UART0_RX, \ + SSD20XD_PINNAME_UART0_TX + +#define SSD20XD_PINNAME_UART1_RX "uart1_rx" +#define SSD20XD_PINNAME_UART1_TX "uart1_tx" + +#define SSD20XD_UART1_NAMES \ + SSD20XD_PINNAME_UART1_RX, \ + SSD20XD_PINNAME_UART1_TX + +#define SSD20XD_OFF_UART0_RX 0x60 +#define SSD20XD_OFF_UART0_TX 0x64 + +#define SSD20XD_UART0_OFFSETS \ + SSD20XD_OFF_UART0_RX, \ + SSD20XD_OFF_UART0_TX + +#define SSD20XD_OFF_UART1_RX 0x68 +#define SSD20XD_OFF_UART1_TX 0x6c + +#define SSD20XD_UART1_OFFSETS \ + SSD20XD_OFF_UART1_RX, \ + SSD20XD_OFF_UART1_TX + +/* + * ssd20x has the same pin names but different ordering + * of the registers that control the gpio. + */ +#define SSD20XD_OFF_SD_D0 0x140 +#define SSD20XD_OFF_SD_D1 0x144 +#define SSD20XD_OFF_SD_D2 0x148 +#define SSD20XD_OFF_SD_D3 0x14c +#define SSD20XD_OFF_SD_CMD 0x150 +#define SSD20XD_OFF_SD_CLK 0x154 + +#define SSD20XD_SD_OFFSETS SSD20XD_OFF_SD_CLK, \ + SSD20XD_OFF_SD_CMD, \ + SSD20XD_OFF_SD_D0, \ + SSD20XD_OFF_SD_D1, \ + SSD20XD_OFF_SD_D2, \ + SSD20XD_OFF_SD_D3 + +static const char * const ssd20xd_names[] = { + FUART_NAMES, + SD_NAMES, + SSD20XD_UART0_NAMES, + SSD20XD_UART1_NAMES, + SSD20XD_TTL_PINNAMES, + SSD20XD_GPIO_NAMES, +}; + +static const unsigned int ssd20xd_offsets[] = { + FUART_OFFSETS, + SSD20XD_SD_OFFSETS, + SSD20XD_UART0_OFFSETS, + SSD20XD_UART1_OFFSETS, + SSD20XD_TTL_OFFSETS, + SSD20XD_GPIO_OFFSETS, +}; + +MSC313_GPIO_CHIPDATA(ssd20xd); #endif struct msc313_gpio { @@ -412,6 +669,10 @@ static const struct of_device_id msc313_gpio_of_match[] = { .compatible = "mstar,msc313-gpio", .data = &msc313_data, }, + { + .compatible = "sstar,ssd20xd-gpio", + .data = &ssd20xd_data, + }, #endif { } }; -- 2.32.0
Now there is gpio support for ssd20xd set the right compatible in the gpio node. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 7a5e28b33f96..6f067da61ba3 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -6,6 +6,11 @@ #include "mstar-infinity2m.dtsi" +&gpio { + compatible = "sstar,ssd20xd-gpio"; + status = "okay"; +}; + &smpctrl { compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; status = "okay"; -- 2.32.0
Add the red and white leds present on the unitv2. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- .../boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index a81684002e45..eb35ce00ae50 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "mstar-infinity2m-ssd202d.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "UnitV2"; compatible = "m5stack,unitv2", "mstar,infinity2m"; @@ -18,6 +20,18 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + white { + gpios = <&gpio SSD20XD_GPIO_GPIO0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "activity"; + }; + red { + gpios = <&gpio SSD20XD_GPIO_GPIO1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; }; &pm_uart { -- 2.32.0
Add a fixed regulator for the "core" (mainly CPU) voltage. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index eb35ce00ae50..4a22b82afbfd 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -32,6 +32,14 @@ red { linux,default-trigger = "heartbeat"; }; }; + + vcc_core: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + }; }; &pm_uart { -- 2.32.0
Add a fixed regulator for the io voltage. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 4a22b82afbfd..314eb37d3be4 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -40,6 +40,14 @@ vcc_core: regulator@0 { regulator-max-microvolt = <900000>; regulator-boot-on; }; + + vcc_io: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; }; &pm_uart { -- 2.32.0
Add a fixed regulator for the DRAM voltage. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 314eb37d3be4..648751a1b27e 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -48,6 +48,14 @@ vcc_io: regulator@1 { regulator-max-microvolt = <3300000>; regulator-boot-on; }; + + vcc_dram: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; }; &pm_uart { -- 2.32.0
Add a GPIO controlled fixed regulator for the Realtek WiFi connected via USB. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 648751a1b27e..525305a3e3ac 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -56,6 +56,14 @@ vcc_dram: regulator@2 { regulator-max-microvolt = <1500000>; regulator-boot-on; }; + + vcc_wifi: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio SSD20XD_GPIO_GPIO14 0>; + }; }; &pm_uart { -- 2.32.0
On Sat, 17 Jul 2021 13:56:18 +0900, Daniel Palmer wrote:
> Add a compatible string for "ssd20xd" for the SigmaStar SSD201
> and SSD202D chips. These chips are the same die with different
> memory bonded so they don't need their own strings.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
On Sat, 17 Jul 2021 13:56:19 +0900, Daniel Palmer wrote:
> Add the gpio offsets for the SSD201 and SSD202D chips.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> include/dt-bindings/gpio/msc313-gpio.h | 71 ++++++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> Add a compatible string for "ssd20xd" for the SigmaStar SSD201
> and SSD202D chips. These chips are the same die with different
> memory bonded so they don't need their own strings.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> Add the gpio offsets for the SSD201 and SSD202D chips.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> - Remove the unneeded assignment of ret before returning it.
> - Remove an unneeded blank line
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> This adds GPIO support for the SSD201 and SSD202D chips.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> Now there is gpio support for ssd20xd set the right compatible in the gpio node.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
> This is a little series to add a compatible string for the Sigmastar
> SSD201 and SSD202D to the msc313 gpio driver, add the specific offsets
> for the pins on these chips, and then a bunch of DT wiring stuff so
> that the LEDs on the M5 stack unitv2 work and it can control the
> power switch for the USB connected.
>
> Daniel Palmer (10):
> dt-bindings: gpio: msc313: Add compatible for ssd20xd
> dt-bindings: gpio: msc313: Add offsets for ssd20xd
> gpio: msc313: Code clean ups
> gpio: msc313: Add support for SSD201 and SSD202D
I suppose Bartosz can just merge the 4 first patches into the
GPIO tree and you can take the rest into the SoC tree?
Yours,
Linus Walleij
Hi Linus, On Fri, 30 Jul 2021 at 19:12, Linus Walleij <linus.walleij@linaro.org> wrote: > On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote: > > Daniel Palmer (10): > > dt-bindings: gpio: msc313: Add compatible for ssd20xd > > dt-bindings: gpio: msc313: Add offsets for ssd20xd > > gpio: msc313: Code clean ups > > gpio: msc313: Add support for SSD201 and SSD202D > > I suppose Bartosz can just merge the 4 first patches into the > GPIO tree Yep. >And you can take the rest into the SoC tree? My plan is to take the rest into a "mstar dts for 5.15" branch along with some other bits and send a PR to Arnd and Olof later on. Thanks for checking out the patches. Cheers, Daniel
Le ven. 30 juil. 2021 à 12:11, Linus Walleij
<linus.walleij@linaro.org> a écrit :
>
> On Sat, Jul 17, 2021 at 6:56 AM Daniel Palmer <daniel@0x0f.com> wrote:
>
> > Now there is gpio support for ssd20xd set the right compatible in the gpio node.
> >
> > Signed-off-by: Daniel Palmer <daniel@0x0f.com>
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Regards,
Romain
+ Bartosz
Hi Linus, Bartosz,
On Fri, 30 Jul 2021 at 19:12, Linus Walleij <linus.walleij@linaro.org> wrote:
> I suppose Bartosz can just merge the 4 first patches into the
> GPIO tree and you can take the rest into the SoC tree?
>
> Yours,
> Linus Walleij
I just noticed I hadn't to'd Bartosz about these. Is there anything I
need to do for the first patches?
Cheers,
Daniel
On Wed, Aug 25, 2021 at 1:50 PM Daniel Palmer <daniel@0x0f.com> wrote:
>
> + Bartosz
>
> Hi Linus, Bartosz,
>
> On Fri, 30 Jul 2021 at 19:12, Linus Walleij <linus.walleij@linaro.org> wrote:
> > I suppose Bartosz can just merge the 4 first patches into the
> > GPIO tree and you can take the rest into the SoC tree?
> >
> > Yours,
> > Linus Walleij
>
> I just noticed I hadn't to'd Bartosz about these. Is there anything I
> need to do for the first patches?
>
> Cheers,
>
> Daniel
I only have a part of this series in my inbox and patchwork doesn't
have it at all - can you resend it with me in Cc?
Bart
Hi Bart,
On Wed, 22 Sept 2021 at 19:20, Bartosz Golaszewski
<bgolaszewski@baylibre.com> wrote:
> I only have a part of this series in my inbox and patchwork doesn't
> have it at all - can you resend it with me in Cc?
Sure. I want to do some fixes to the DTS bits at the end of the series
so I will send it as a v2. The gpio code parts will be unchanged.
Cheers,
Daniel
On Wed, Sep 22, 2021 at 1:21 PM Bartosz Golaszewski <bgolaszewski@baylibre.com> wrote: > On Wed, Aug 25, 2021 at 1:50 PM Daniel Palmer <daniel@0x0f.com> wrote: > > Hi Linus, Bartosz, ... > > I just noticed I hadn't to'd Bartosz about these. Is there anything I > > need to do for the first patches? > > I only have a part of this series in my inbox and patchwork doesn't > have it at all - can you resend it with me in Cc? Have you tried to use the `b4` tool? It is capable of getting everything from the lore archive. -- With Best Regards, Andy Shevchenko
On Wed, Sep 22, 2021 at 12:52 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Wed, Sep 22, 2021 at 1:21 PM Bartosz Golaszewski
> <bgolaszewski@baylibre.com> wrote:
> > On Wed, Aug 25, 2021 at 1:50 PM Daniel Palmer <daniel@0x0f.com> wrote:
> > > Hi Linus, Bartosz,
>
> ...
>
> > > I just noticed I hadn't to'd Bartosz about these. Is there anything I
> > > need to do for the first patches?
> >
> > I only have a part of this series in my inbox and patchwork doesn't
> > have it at all - can you resend it with me in Cc?
>
> Have you tried to use the `b4` tool? It is capable of getting
> everything from the lore archive.
>
I haven't tried it because I have never heard of it. :) Thanks for the heads-up.
At the same time - is it too much to ask of people to just use
scripts/get_maintainer.pl? It's so much easier to just actually get
the patches in my inbox than to have to look for them manually.
Bartosz
On Wed, Sep 22, 2021 at 3:50 PM Bartosz Golaszewski <bgolaszewski@baylibre.com> wrote: > On Wed, Sep 22, 2021 at 12:52 PM Andy Shevchenko > <andy.shevchenko@gmail.com> wrote: > > On Wed, Sep 22, 2021 at 1:21 PM Bartosz Golaszewski > > <bgolaszewski@baylibre.com> wrote: > > > On Wed, Aug 25, 2021 at 1:50 PM Daniel Palmer <daniel@0x0f.com> wrote: ... > > > I only have a part of this series in my inbox and patchwork doesn't > > > have it at all - can you resend it with me in Cc? > > > > Have you tried to use the `b4` tool? It is capable of getting > > everything from the lore archive. > > I haven't tried it because I have never heard of it. :) Thanks for the heads-up. You're welcome! > At the same time - is it too much to ask of people to just use > scripts/get_maintainer.pl? It's so much easier to just actually get > the patches in my inbox than to have to look for them manually. Of course not. I completely agree with you on the point. Btw, I advertise a script I wrote [1] exactly due to misses of this in the past. [1]: https://github.com/andy-shev/home-bin-tools/blob/master/ge2maintainer.sh -- With Best Regards, Andy Shevchenko
Hi Bartosz, On Wed, 22 Sept 2021 at 21:50, Bartosz Golaszewski <bgolaszewski@baylibre.com> wrote: > > > I only have a part of this series in my inbox and patchwork doesn't > > > have it at all - can you resend it with me in Cc? I just checked and the series is in patchwork - https://patchwork.ozlabs.org/project/linux-gpio/patch/20210717045627.1739959-2-daniel@0x0f.com/ Unless I got the wrong patchwork? > At the same time - is it too much to ask of people to just use > scripts/get_maintainer.pl? Sorry about that. scripts/get_maintainer.pl can return tons of people, I get cc'd on stuff I have no idea about because I touched a line somewhere, so I generally try to work out who needs to see a series from the places touched and the get_maintainer.pl output instead of just spamming everyone. In this case I thought Linus was the subsystem maintainer as he took the initial series for this driver and I took the mail recipients list from that series and pasted it in. I'll be more careful next time. Thanks, Daniel
On Wed, Sep 22, 2021 at 2:50 PM Bartosz Golaszewski <bgolaszewski@baylibre.com> wrote: > On Wed, Sep 22, 2021 at 12:52 PM Andy Shevchenko > <andy.shevchenko@gmail.com> wrote: > > Have you tried to use the `b4` tool? It is capable of getting > > everything from the lore archive. > > I haven't tried it because I have never heard of it. :) Thanks for the heads-up. I use this all the time, it is awesome. Yours, Linus Walleij