From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751496AbdINNy7 (ORCPT ); Thu, 14 Sep 2017 09:54:59 -0400 Received: from mail-it0-f43.google.com ([209.85.214.43]:46699 "EHLO mail-it0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751392AbdINNy5 (ORCPT ); Thu, 14 Sep 2017 09:54:57 -0400 X-Google-Smtp-Source: AOwi7QCT0iuDDm+NCkOrQcFjCWo3HfrO/VXvx753jZeyoYGjtQ9Hpj8Mgy5KlM3zVNQ5mkSW5gW5OwMQCjncAv49jZk= MIME-Version: 1.0 In-Reply-To: <20170901185736.28051-1-thierry.reding@gmail.com> References: <20170901185736.28051-1-thierry.reding@gmail.com> From: Linus Walleij Date: Thu, 14 Sep 2017 15:54:56 +0200 Message-ID: Subject: Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked infrastructure To: Thierry Reding Cc: Jonathan Hunter , "linux-gpio@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , ext Tony Lindgren Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding wrote: > here's the latest series of patches that implement the tighter IRQ chip > integration as well as the banked GPIO infrastructure that we had > discussed a couple of weeks/months back. Yes it has become really tasty now, don't you think :) I really like the series. Banks are handled in the core, exactly as I wanted. I will likely go in and change some things I don't like, like switching num_pins in the bank to num_lines. I have preferred that terminology to avoid confusion with pin control. So GPIO chips have lines, not pins. But it's so minor that I can fix it up if you don't want to. We also need to go in and patch Documentation/gpio/driver.txt to represent the current best practice. But that can be later, separate patch. > The first couple of patches are mostly preparatory work in order to > consolidate all IRQ chip related fields in a new structure and create > the base functionality for adding IRQ chips. > > After that, I've added the Tegra186 GPIO support patch that makes use of > the new tight integration. > > To round things off the new banked GPIO infrastructure is added (along > with some more preparatory work), followed by the conversion of the two > Tegra GPIO drivers to the new infrastructure. I have put all on a branch for pushing to the test builders to begin with. Then I plan to make one branch with all infrastructure patches (patches 1-10, 12-14) and pull that into devel, then apply patch 11 and 15-16 directly on devel. That way other subsystems (pinctrl ...) can pull in the infrastructure for people adding new gpiochips this cycle. > Any thoughts on this? I'd like to target 4.15 with this, Me, too. > unless you'd be > willing to take this into 4.14, which I doubt at this point. The absence > of a GPIO driver has been hampering Tegra186 support upstream for a > while now, so it'd be good to make progress on this. Sorry about that. Let's move ahead with this now, it is neat and clean. What I want (as maintainer) is a bit of fingerpointing at the drivers that need to be converted to use the new banking infrastructure so they don't stay with their old crappy design pattern. OMAP is a clear candidate right? (Added Tony to CC...) Who else? Yours, Linus Walleij