From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF55CC47085 for ; Tue, 25 May 2021 00:07:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 911CD60FE6 for ; Tue, 25 May 2021 00:07:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229906AbhEYAI3 (ORCPT ); Mon, 24 May 2021 20:08:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbhEYAIZ (ORCPT ); Mon, 24 May 2021 20:08:25 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FA50C061574 for ; Mon, 24 May 2021 17:06:55 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id j10so43103129lfb.12 for ; Mon, 24 May 2021 17:06:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kMpOljGnfPeM78kPggxibkmCL00Y57PzO5ZmaEV0BXY=; b=MewdMHu8pSiz9xtZOKCGO2UN+t5TiiRcBHH1a51nLZOQ930DNpl6gJPaV2XGMGRFVM e/50I9+o6cNImkcNqVmAHX1IG1yNlF+DM2eszkohBGYtUWYHCehhn6ipxRJhfR/9wxcu yp+JYSiP05pJjGHOkI4oqCGDNxIX+rKjQWIB2oIlP8QoqW7i9RYKKn76Ir0HgL2Vkyol qZ8LWSZkflFyvnqM1aEJNpem1C1r3uEIL83lAtsZ+Qs1MafIqT6TVc99DPwYyg6+YxgP n9xGP/9mCT8suXOUCn2J9jmJLenG4SLFB9g1rhAIWDXz8kpASz65DzXqXMLjzllemIH9 menQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kMpOljGnfPeM78kPggxibkmCL00Y57PzO5ZmaEV0BXY=; b=D4Df+1BaPDzG3cO6nfssDDKTIMenftZhgO7t3ogzoLTOErUjzYkFjffrBl5qX9IebX omXlaAqYdM5gVT1ei+jO7bKNPo3GGW5lndNCWVDS34el8P61TKFl2rWUYRAxePtCYqAo DOv+O1qmRmyr/OPFST8ScVTiL7FgyH74Zd8gCmZMtWe4Fuo6Zs22/6+EmuwYfcxHFoAL 5ZHPCUiWuQQbMav5YHwdPJyPVQXhUBtYDURXfISvpVoXOYwP0arSN9G/Lt+JEFZvGX8V VWJbVkHmOPjU52joIm9ysCMVZ0+o0eMSNNlmQuC3Y3FMAqxFfWYhS7UH2iWPqdoX6e8J IpoQ== X-Gm-Message-State: AOAM530K28he9yshJ7Bvv+0LTzTlBHyzPID9nvYGs7Aqa3MD5XykBHnk qz1J4fuCLb2vbNl4R/AktHr6Pb9vHRTCbmeGSfp3rA== X-Google-Smtp-Source: ABdhPJx94W96U3rvN6Jk3W8XwfHaYZxs8wqy2iOgobL2N4vLXoIZf9tS5BonEJmR9TdQKSwTD05BGaGxDwMtobVK2RA= X-Received: by 2002:a05:6512:1185:: with SMTP id g5mr12286057lfr.586.1621901213604; Mon, 24 May 2021 17:06:53 -0700 (PDT) MIME-Version: 1.0 References: <20210510063602.505829-1-jay.xu@rock-chips.com> <20210510063602.505829-4-jay.xu@rock-chips.com> In-Reply-To: <20210510063602.505829-4-jay.xu@rock-chips.com> From: Linus Walleij Date: Tue, 25 May 2021 02:06:43 +0200 Message-ID: Subject: Re: [PATCH 3/7] gpio: separate gpio driver from pinctrl-rockchip driver To: Jianqun Xu Cc: =?UTF-8?Q?Heiko_St=C3=BCbner?= , Rob Herring , "open list:GPIO SUBSYSTEM" , "open list:ARM/Rockchip SoC..." , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 10, 2021 at 8:36 AM Jianqun Xu wrote: > Separate the gpio driver from the pinctrl driver. > > Signed-off-by: Jianqun Xu Overall this is very good and should be applied. > +#include "../pinctrl/core.h" > +#include "../pinctrl/pinctrl-rockchip.h" Please explain in a comment exactly why you need to include these files. I think it should be the goal to get rid of this dependency. It seems that the driver can be further simplified using GPIO_GENERIC but we can deal with this later, once it is separate. > +static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, > + unsigned long config) > +{ > + enum pin_config_param param = pinconf_to_config_param(config); > + > + switch (param) { > + case PIN_CONFIG_INPUT_DEBOUNCE: > + rockchip_gpio_set_debounce(gc, offset, true); (...) > + .set_config = rockchip_gpio_set_config, Can't you just use gpiochip_generic_config() and rely on the pinctrl back-end to deal with this? > + .to_irq = rockchip_gpio_to_irq, Normally this should not be needed with GPIOLIB_IRQCHIP but since you are refactoring an existing driver it is acceptable to keep for now. Yours, Linus Walleij