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* [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K
@ 2017-06-12 15:34 Gregory CLEMENT
  2017-06-12 15:34 ` [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage Gregory CLEMENT
                   ` (8 more replies)
  0 siblings, 9 replies; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

Hi,

This third version would allow to apply the series without any
conflict:

- This time the series is rebased on gpio/for-next to avoid conflict
  with already applied patches.

- The documentation part has been removed from this series and I will
  asked to Rob Herring to apply through the device tree subsystem.

Thanks to this there is no external dependencies except the dts part
that have to be merged through the mvebu tree.

The first patch is a fix that was already posted.

Then the first part of the series is adding the support for the pin
controllers found on the Marvell Armada 7K/8K.

These controllers are compatible with the ones found on the ARM32
mvebu SoCs. However, the pinctrl node in the device tree of theses
SoCs are child of a syscon. So for them we will reuse the regmap
support introduced by Russell King.

Each component of the Armada 7K and 8K comes with their own pin
controller, that's why we have 2 new drivers: one for the CP110 and
one for the AP806.

The second part of the series extends the mvebu gpio driver to support
the gpio controllers found on the Marvell Armada 7K/8K SoCs.

The gpio controllers used on the Marvell Armada 7K/8K SoCs are the
same that the ones used on the ARM32 mvebu SoCs. However, the pinctrl
node in the device tree of theses SoCs are child of a syscon.

Thanks,

Gregory

Changelog:
v2 -> v3

- Rebased on gpio/for-next.

- Added the fix "gpio: mvebu: fix regmap_update_bits usage" with the
  tested-by and reviewed-by flag

- Removed the binding documentation patch that will be applied through
  an other path.

v1 -> v2:

- Merged of the pinctrl and gpio series.

- Rebased on next-20170531 (which contains gpio and pinctrl commit
  already applied).

- Removed already applied patches.

- Remove the modular support of the drivers, suggested by Paul
  Gortmaker.

- Added tested-by from Thomas Petazzoni.

- Added acked-by from Rob Herring.

Gregory CLEMENT (6):
  gpio: mvebu: fix regmap_update_bits usage
  pinctrl: mvebu: remove the offset property for regmap
  arm64: marvell: enable the Armada 7K/8K pinctrl driver
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  gpio: mvebu: Add support for the Armada 7K/8K SoCs
  arm64: dts: marvell: add gpio support for Armada 7K/8K

Hanna Hawa (2):
  pinctrl: mvebu: add driver for Armada AP806 pinctrl
  pinctrl: mvebu: add driver for Armada CP110 pinctrl

Russell King (1):
  pinctrl: avoid PLAT_ORION dependency

 arch/arm64/Kconfig.platforms                         |   2 +-
 arch/arm64/boot/dts/marvell/armada-7020.dtsi         |   2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi         |   2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi         |  68 +-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi         |   3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi         |   3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi         |  76 +-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi        |  14 +-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi |  21 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  |  22 +-
 drivers/gpio/gpio-mvebu.c                            | 216 ++--
 drivers/pinctrl/mvebu/Kconfig                        |  12 +-
 drivers/pinctrl/mvebu/Makefile                       |   2 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c         | 140 ++-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c         | 687 ++++++++++++-
 drivers/pinctrl/mvebu/pinctrl-mvebu.c                |   6 +-
 drivers/pinctrl/mvebu/pinctrl-mvebu.h                |   2 +-
 17 files changed, 1189 insertions(+), 89 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

base-commit: 77fd50d14eb4a48d00cee84a7beae174f8011157
-- 
git-series 0.9.1

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:18   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap Gregory CLEMENT
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri,
	Chris Packham, Ralph Sennhauser

In some place in the driver regmap_update_bits was misused. Indeed the
last argument is not the value of the bit (or group of bits) itself but
the mask value inside the register.

So when setting the bit N, then the value must be BIT(N) and not 1.

CC: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
CC: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/gpio/gpio-mvebu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 4aec8762fdc5..d5939913d310 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -341,7 +341,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
 		return ret;
 
 	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
-			   BIT(pin), 1);
+			   BIT(pin), BIT(pin));
 
 	return 0;
 }
@@ -503,7 +503,7 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	case IRQ_TYPE_EDGE_FALLING:
 	case IRQ_TYPE_LEVEL_LOW:
 		regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
-				   BIT(pin), 1);
+				   BIT(pin), BIT(pin));
 		break;
 	case IRQ_TYPE_EDGE_BOTH: {
 		u32 data_in, in_pol, val;
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
  2017-06-12 15:34 ` [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:20   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency Gregory CLEMENT
                   ` (6 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

The offset property of the pinctrl node, when a regmap is used in the
device tree, was never used nor documented in the binding. Moreover, the
compatible string is enough to let the driver know which offset using.

So this patch removes the property and move the information at the driver
level.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-mvebu.c | 6 +-----
 drivers/pinctrl/mvebu/pinctrl-mvebu.h | 2 +-
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index e4dda12d371a..163d4614b0f8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -810,21 +810,17 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
 }
 
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
-				      struct device *syscon_dev)
+				      struct device *syscon_dev, u32 offset)
 {
 	struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
 	struct mvebu_mpp_ctrl_data *mpp_data;
 	struct regmap *regmap;
-	u32 offset;
 	int i;
 
 	regmap = syscon_node_to_regmap(syscon_dev->of_node);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-	if (of_property_read_u32(pdev->dev.of_node, "offset", &offset))
-		return -EINVAL;
-
 	mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data),
 				GFP_KERNEL);
 	if (!mpp_data)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index c90704e74884..75bba436bf59 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -210,6 +210,6 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 int mvebu_pinctrl_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev);
 int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
-				      struct device *syscon_dev);
+				      struct device *syscon_dev, u32 offset);
 
 #endif
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
  2017-06-12 15:34 ` [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage Gregory CLEMENT
  2017-06-12 15:34 ` [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:21   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver Gregory CLEMENT
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

From: Russell King <rmk+kernel@armlinux.org.uk>

Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/Kconfig | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 5bade32d3089..8cb444b60ae9 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,5 +1,3 @@
-if PLAT_ORION
-
 config PINCTRL_MVEBU
 	bool
 	select PINMUX
@@ -38,8 +36,6 @@ config PINCTRL_ORION
 	bool
 	select PINCTRL_MVEBU
 
-endif
-
 config PINCTRL_ARMADA_37XX
        bool
        select GENERIC_PINCONF
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (2 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:22   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl Gregory CLEMENT
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

This commit makes sure the drivers for the Armada 7K/8K pin controllers
are enabled.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/Kconfig.platforms | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 73272f43ca01..bb064c42e74c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -113,6 +113,8 @@ config ARCH_MVEBU
 	select OF_GPIO
 	select PINCTRL
 	select PINCTRL_ARMADA_37XX
+	select PINCTRL_ARMADA_AP806
+	select PINCTRL_ARMADA_CP110
 	help
 	  This enables support for Marvell EBU familly, including:
 	   - Armada 3700 SoC Family
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (3 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:23   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl Gregory CLEMENT
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri,
	Hanna Hawa

From: Hanna Hawa <hannah@marvell.com>

This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.

Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl changes
 - converted to simple_mmio
 - removed unimplemented .remove function
 - removed DTS description
  - converted  to use syscon/regmap
 --rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/Kconfig                |   4 +-
 drivers/pinctrl/mvebu/Makefile               |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c | 140 ++++++++++++++++++++-
 3 files changed, 145 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-ap806.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 8cb444b60ae9..0e0b009f2b71 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -28,6 +28,10 @@ config PINCTRL_ARMADA_39X
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_AP806
+	bool
+	select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
 	bool
 	select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 60c245a60f39..455db274b53d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
+obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
new file mode 100644
index 000000000000..66e442260a4e
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
@@ -0,0 +1,140 @@
+/*
+ * Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Hanna Hawa <hannah@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "clk"),
+		 MPP_FUNCTION(3, "spi0",    "clk")),
+	MPP_MODE(1,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "cmd"),
+		 MPP_FUNCTION(3, "spi0",    "miso")),
+	MPP_MODE(2,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d0"),
+		 MPP_FUNCTION(3, "spi0",    "mosi")),
+	MPP_MODE(3,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d1"),
+		 MPP_FUNCTION(3, "spi0",    "cs0n")),
+	MPP_MODE(4,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d2"),
+		 MPP_FUNCTION(3, "i2c0",    "sda")),
+	MPP_MODE(5,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d3"),
+		 MPP_FUNCTION(3, "i2c0",    "sdk")),
+	MPP_MODE(6,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "ds")),
+	MPP_MODE(7,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d4"),
+		 MPP_FUNCTION(3, "uart1",   "rxd")),
+	MPP_MODE(8,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d5"),
+		 MPP_FUNCTION(3, "uart1",   "txd")),
+	MPP_MODE(9,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d6"),
+		 MPP_FUNCTION(3, "spi0",    "cs1n")),
+	MPP_MODE(10,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "d7")),
+	MPP_MODE(11,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(3, "uart0",   "txd")),
+	MPP_MODE(12,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(1, "sdio",    "pw_off"),
+		 MPP_FUNCTION(2, "sdio",    "hw_rst")),
+	MPP_MODE(13,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(14,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(15,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(16,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(17,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(18,
+		 MPP_FUNCTION(0, "gpio",    NULL)),
+	MPP_MODE(19,
+		 MPP_FUNCTION(0, "gpio",    NULL),
+		 MPP_FUNCTION(3, "uart0",   "rxd"),
+		 MPP_FUNCTION(4, "sdio",    "pw_off")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_ap806_pinctrl_info;
+
+static const struct of_device_id armada_ap806_pinctrl_of_match[] = {
+	{
+		.compatible = "marvell,ap806-pinctrl",
+	},
+	{ },
+};
+
+static const struct mvebu_mpp_ctrl armada_ap806_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 19, NULL, mvebu_regmap_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range armada_ap806_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 20),
+};
+
+static int armada_ap806_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_ap806_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(armada_ap806_pinctrl_of_match, &pdev->dev);
+
+	if (!match || !pdev->dev.parent)
+		return -ENODEV;
+
+	soc->variant = 0; /* no variants for Armada AP806 */
+	soc->controls = armada_ap806_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(armada_ap806_mpp_controls);
+	soc->gpioranges = armada_ap806_mpp_gpio_ranges;
+	soc->ngpioranges = ARRAY_SIZE(armada_ap806_mpp_gpio_ranges);
+	soc->modes = armada_ap806_mpp_modes;
+	soc->nmodes = armada_ap806_mpp_controls[0].npins;
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
+}
+
+static struct platform_driver armada_ap806_pinctrl_driver = {
+	.driver = {
+		.name = "armada-ap806-pinctrl",
+		.of_match_table = of_match_ptr(armada_ap806_pinctrl_of_match),
+	},
+	.probe = armada_ap806_pinctrl_probe,
+};
+
+builtin_platform_driver(armada_ap806_pinctrl_driver);
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (4 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:24   ` Linus Walleij
  2017-06-16  9:26   ` Linus Walleij
  2017-06-12 15:34 ` [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K Gregory CLEMENT
                   ` (2 subsequent siblings)
  8 siblings, 2 replies; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri,
	Hanna Hawa, Grzegorz Jaszczyk

From: Hanna Hawa <hannah@marvell.com>

This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).

The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.

Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>

[updated for mvebu pinctrl and 4.9 changes:
 - converted to simple_mmio
 - converted to syscon/regmap
 - removed unimplemented .remove function
 - dropped DTS changes
 - defered gpio ranges to DT
 - fixed warning
 - properly set soc->nmodes
 -- rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

[ - rebased on 4.12-rc1
  - fixed the 80 character limit for mvebu_mpp_mode array
  - aligned the compatible name on the ones already used
  - fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/pinctrl/mvebu/Kconfig                |   4 +-
 drivers/pinctrl/mvebu/Makefile               |   1 +-
 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 687 ++++++++++++++++++++-
 3 files changed, 692 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 0e0b009f2b71..d9773b77ff9f 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -32,6 +32,10 @@ config PINCTRL_ARMADA_AP806
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_CP110
+	bool
+	select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
 	bool
 	select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 455db274b53d..5b03fd55e28d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
 obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
 obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
+obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ARMADA_37XX)  += pinctrl-armada-37xx.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
new file mode 100644
index 000000000000..7f85beb45482
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -0,0 +1,687 @@
+/*
+ * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa <hannah@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-mvebu.h"
+
+/*
+ * Even if the pin controller is the same the MMP available depend on the SoC
+ * integration.
+ *  - In Armada7K (single CP) almost all the MPPs are available (except the
+ *    MMP 39 to 43)
+ *  - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
+ *    CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
+ *    V_ARMADA_8K_CPS) set which MPP is available to the CPx.
+ * The x_PLUS enum mean that the MPP available for CPx and for Armada70x0
+ */
+enum {
+	V_ARMADA_7K = BIT(0),
+	V_ARMADA_8K_CPM = BIT(1),
+	V_ARMADA_8K_CPS = BIT(2),
+	V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
+	V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
+};
+
+static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ale1"),
+		 MPP_FUNCTION(2,	"au",		"i2smclk"),
+		 MPP_FUNCTION(3,	"ge0",		"rxd3"),
+		 MPP_FUNCTION(4,	"tdm",		"pclk"),
+		 MPP_FUNCTION(6,	"ptp",		"pulse"),
+		 MPP_FUNCTION(7,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(8,	"uart0",	"rxd"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"ge",		"mdio")),
+	MPP_MODE(1,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ale0"),
+		 MPP_FUNCTION(2,	"au",		"i2sdo_spdifo"),
+		 MPP_FUNCTION(3,	"ge0",		"rxd2"),
+		 MPP_FUNCTION(4,	"tdm",		"drx"),
+		 MPP_FUNCTION(6,	"ptp",		"clk"),
+		 MPP_FUNCTION(7,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(8,	"uart0",	"txd"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"ge",		"mdc")),
+	MPP_MODE(2,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad15"),
+		 MPP_FUNCTION(2,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(3,	"ge0",		"rxd1"),
+		 MPP_FUNCTION(4,	"tdm",		"dtx"),
+		 MPP_FUNCTION(5,	"mss_uart",	"rxd"),
+		 MPP_FUNCTION(6,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(7,	"i2c1",		"sck"),
+		 MPP_FUNCTION(8,	"uart1",	"rxd"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"xg",		"mdc")),
+	MPP_MODE(3,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad14"),
+		 MPP_FUNCTION(2,	"au",		"i2slrclk"),
+		 MPP_FUNCTION(3,	"ge0",		"rxd0"),
+		 MPP_FUNCTION(4,	"tdm",		"fsync"),
+		 MPP_FUNCTION(5,	"mss_uart",	"txd"),
+		 MPP_FUNCTION(6,	"pcie",		"rstoutn"),
+		 MPP_FUNCTION(7,	"i2c1",		"sda"),
+		 MPP_FUNCTION(8,	"uart1",	"txd"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"xg",		"mdio")),
+	MPP_MODE(4,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad13"),
+		 MPP_FUNCTION(2,	"au",		"i2sbclk"),
+		 MPP_FUNCTION(3,	"ge0",		"rxctl"),
+		 MPP_FUNCTION(4,	"tdm",		"rstn"),
+		 MPP_FUNCTION(5,	"mss_uart",	"rxd"),
+		 MPP_FUNCTION(6,	"uart1",	"cts"),
+		 MPP_FUNCTION(7,	"pcie0",	"clkreq"),
+		 MPP_FUNCTION(8,	"uart3",	"rxd"),
+		 MPP_FUNCTION(10,	"ge",		"mdc")),
+	MPP_MODE(5,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad12"),
+		 MPP_FUNCTION(2,	"au",		"i2sdi"),
+		 MPP_FUNCTION(3,	"ge0",		"rxclk"),
+		 MPP_FUNCTION(4,	"tdm",		"intn"),
+		 MPP_FUNCTION(5,	"mss_uart",	"txd"),
+		 MPP_FUNCTION(6,	"uart1",	"rts"),
+		 MPP_FUNCTION(7,	"pcie1",	"clkreq"),
+		 MPP_FUNCTION(8,	"uart3",	"txd"),
+		 MPP_FUNCTION(10,	"ge",		"mdio")),
+	MPP_MODE(6,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad11"),
+		 MPP_FUNCTION(3,	"ge0",		"txd3"),
+		 MPP_FUNCTION(4,	"spi0",		"csn2"),
+		 MPP_FUNCTION(5,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(6,	"sata1",	"present_act"),
+		 MPP_FUNCTION(7,	"pcie2",	"clkreq"),
+		 MPP_FUNCTION(8,	"uart0",	"rxd"),
+		 MPP_FUNCTION(9,	"ptp",		"pulse")),
+	MPP_MODE(7,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad10"),
+		 MPP_FUNCTION(3,	"ge0",		"txd2"),
+		 MPP_FUNCTION(4,	"spi0",		"csn1"),
+		 MPP_FUNCTION(5,	"spi1",		"csn1"),
+		 MPP_FUNCTION(6,	"sata0",	"present_act"),
+		 MPP_FUNCTION(7,	"led",		"data"),
+		 MPP_FUNCTION(8,	"uart0",	"txd"),
+		 MPP_FUNCTION(9,	"ptp",		"clk")),
+	MPP_MODE(8,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad9"),
+		 MPP_FUNCTION(3,	"ge0",		"txd1"),
+		 MPP_FUNCTION(4,	"spi0",		"csn0"),
+		 MPP_FUNCTION(5,	"spi1",		"csn0"),
+		 MPP_FUNCTION(6,	"uart0",	"cts"),
+		 MPP_FUNCTION(7,	"led",		"stb"),
+		 MPP_FUNCTION(8,	"uart2",	"rxd"),
+		 MPP_FUNCTION(9,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(10,	"synce1",	"clk")),
+	MPP_MODE(9,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad8"),
+		 MPP_FUNCTION(3,	"ge0",		"txd0"),
+		 MPP_FUNCTION(4,	"spi0",		"mosi"),
+		 MPP_FUNCTION(5,	"spi1",		"mosi"),
+		 MPP_FUNCTION(7,	"pcie",		"rstoutn"),
+		 MPP_FUNCTION(10,	"synce2",	"clk")),
+	MPP_MODE(10,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"readyn"),
+		 MPP_FUNCTION(3,	"ge0",		"txctl"),
+		 MPP_FUNCTION(4,	"spi0",		"miso"),
+		 MPP_FUNCTION(5,	"spi1",		"miso"),
+		 MPP_FUNCTION(6,	"uart0",	"cts"),
+		 MPP_FUNCTION(7,	"sata1",	"present_act")),
+	MPP_MODE(11,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"wen1"),
+		 MPP_FUNCTION(3,	"ge0",		"txclkout"),
+		 MPP_FUNCTION(4,	"spi0",		"clk"),
+		 MPP_FUNCTION(5,	"spi1",		"clk"),
+		 MPP_FUNCTION(6,	"uart0",	"rts"),
+		 MPP_FUNCTION(7,	"led",		"clk"),
+		 MPP_FUNCTION(8,	"uart2",	"txd"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act")),
+	MPP_MODE(12,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"clk_out"),
+		 MPP_FUNCTION(2,	"nf",		"rbn1"),
+		 MPP_FUNCTION(3,	"spi1",		"csn1"),
+		 MPP_FUNCTION(4,	"ge0",		"rxclk")),
+	MPP_MODE(13,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"burstn"),
+		 MPP_FUNCTION(2,	"nf",		"rbn0"),
+		 MPP_FUNCTION(3,	"spi1",		"miso"),
+		 MPP_FUNCTION(4,	"ge0",		"rxctl"),
+		 MPP_FUNCTION(8,	"mss_spi",	"miso")),
+	MPP_MODE(14,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"bootcsn"),
+		 MPP_FUNCTION(2,	"dev",		"csn0"),
+		 MPP_FUNCTION(3,	"spi1",		"csn0"),
+		 MPP_FUNCTION(4,	"spi0",		"csn3"),
+		 MPP_FUNCTION(5,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(6,	"spi0",		"miso"),
+		 MPP_FUNCTION(7,	"sata0",	"present_act"),
+		 MPP_FUNCTION(8,	"mss_spi",	"csn")),
+	MPP_MODE(15,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad7"),
+		 MPP_FUNCTION(3,	"spi1",		"mosi"),
+		 MPP_FUNCTION(6,	"spi0",		"mosi"),
+		 MPP_FUNCTION(8,	"mss_spi",	"mosi"),
+		 MPP_FUNCTION(11,	"ptp",		"pulse_cp2cp")),
+	MPP_MODE(16,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad6"),
+		 MPP_FUNCTION(3,	"spi1",		"clk"),
+		 MPP_FUNCTION(8,	"mss_spi",	"clk")),
+	MPP_MODE(17,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad5"),
+		 MPP_FUNCTION(4,	"ge0",		"txd3")),
+	MPP_MODE(18,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad4"),
+		 MPP_FUNCTION(4,	"ge0",		"txd2"),
+		 MPP_FUNCTION(11,	"ptp",		"clk_cp2cp")),
+	MPP_MODE(19,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad3"),
+		 MPP_FUNCTION(4,	"ge0",		"txd1"),
+		 MPP_FUNCTION(11,	"wakeup",	"out_cp2cp")),
+	MPP_MODE(20,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad2"),
+		 MPP_FUNCTION(4,	"ge0",		"txd0")),
+	MPP_MODE(21,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad1"),
+		 MPP_FUNCTION(4,	"ge0",		"txctl"),
+		 MPP_FUNCTION(11,	"sei",		"in_cp2cp")),
+	MPP_MODE(22,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"ad0"),
+		 MPP_FUNCTION(4,	"ge0",		"txclkout"),
+		 MPP_FUNCTION(11,	"wakeup",	"in_cp2cp")),
+	MPP_MODE(23,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"a1"),
+		 MPP_FUNCTION(5,	"au",		"i2smclk"),
+		 MPP_FUNCTION(11,	"link",		"rd_in_cp2cp")),
+	MPP_MODE(24,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"a0"),
+		 MPP_FUNCTION(5,	"au",		"i2slrclk")),
+	MPP_MODE(25,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"oen"),
+		 MPP_FUNCTION(5,	"au",		"i2sdo_spdifo")),
+	MPP_MODE(26,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"wen0"),
+		 MPP_FUNCTION(5,	"au",		"i2sbclk")),
+	MPP_MODE(27,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"csn0"),
+		 MPP_FUNCTION(2,	"spi1",		"miso"),
+		 MPP_FUNCTION(3,	"mss_gpio4",	NULL),
+		 MPP_FUNCTION(4,	"ge0",		"rxd3"),
+		 MPP_FUNCTION(5,	"spi0",		"csn4"),
+		 MPP_FUNCTION(8,	"ge",		"mdio"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"uart0",	"rts"),
+		 MPP_FUNCTION(11,	"rei",		"in_cp2cp")),
+	MPP_MODE(28,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"csn1"),
+		 MPP_FUNCTION(2,	"spi1",		"csn0"),
+		 MPP_FUNCTION(3,	"mss_gpio5",	NULL),
+		 MPP_FUNCTION(4,	"ge0",		"rxd2"),
+		 MPP_FUNCTION(5,	"spi0",		"csn5"),
+		 MPP_FUNCTION(6,	"pcie2",	"clkreq"),
+		 MPP_FUNCTION(7,	"ptp",		"pulse"),
+		 MPP_FUNCTION(8,	"ge",		"mdc"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"uart0",	"cts"),
+		 MPP_FUNCTION(11,	"led",		"data")),
+	MPP_MODE(29,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"csn2"),
+		 MPP_FUNCTION(2,	"spi1",		"mosi"),
+		 MPP_FUNCTION(3,	"mss_gpio6",	NULL),
+		 MPP_FUNCTION(4,	"ge0",		"rxd1"),
+		 MPP_FUNCTION(5,	"spi0",		"csn6"),
+		 MPP_FUNCTION(6,	"pcie1",	"clkreq"),
+		 MPP_FUNCTION(7,	"ptp",		"clk"),
+		 MPP_FUNCTION(8,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"uart0",	"rxd"),
+		 MPP_FUNCTION(11,	"led",		"stb")),
+	MPP_MODE(30,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"csn3"),
+		 MPP_FUNCTION(2,	"spi1",		"clk"),
+		 MPP_FUNCTION(3,	"mss_gpio7",	NULL),
+		 MPP_FUNCTION(4,	"ge0",		"rxd0"),
+		 MPP_FUNCTION(5,	"spi0",		"csn7"),
+		 MPP_FUNCTION(6,	"pcie0",	"clkreq"),
+		 MPP_FUNCTION(7,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(8,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"uart0",	"txd"),
+		 MPP_FUNCTION(11,	"led",		"clk")),
+	MPP_MODE(31,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"dev",		"a2"),
+		 MPP_FUNCTION(3,	"mss_gpio4",	NULL),
+		 MPP_FUNCTION(6,	"pcie",		"rstoutn"),
+		 MPP_FUNCTION(8,	"ge",		"mdc")),
+	MPP_MODE(32,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mii",		"col"),
+		 MPP_FUNCTION(2,	"mii",		"txerr"),
+		 MPP_FUNCTION(3,	"mss_spi",	"miso"),
+		 MPP_FUNCTION(4,	"tdm",		"drx"),
+		 MPP_FUNCTION(5,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(6,	"au",		"i2sdi"),
+		 MPP_FUNCTION(7,	"ge",		"mdio"),
+		 MPP_FUNCTION(8,	"sdio",		"v18_en"),
+		 MPP_FUNCTION(9,	"pcie1",	"clkreq"),
+		 MPP_FUNCTION(10,	"mss_gpio0",	NULL)),
+	MPP_MODE(33,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mii",		"txclk"),
+		 MPP_FUNCTION(2,	"sdio",		"pwr10"),
+		 MPP_FUNCTION(3,	"mss_spi",	"csn"),
+		 MPP_FUNCTION(4,	"tdm",		"fsync"),
+		 MPP_FUNCTION(5,	"au",		"i2smclk"),
+		 MPP_FUNCTION(6,	"sdio",		"bus_pwr"),
+		 MPP_FUNCTION(8,	"xg",		"mdio"),
+		 MPP_FUNCTION(9,	"pcie2",	"clkreq"),
+		 MPP_FUNCTION(10,	"mss_gpio1",	NULL)),
+	MPP_MODE(34,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mii",		"rxerr"),
+		 MPP_FUNCTION(2,	"sdio",		"pwr11"),
+		 MPP_FUNCTION(3,	"mss_spi",	"mosi"),
+		 MPP_FUNCTION(4,	"tdm",		"dtx"),
+		 MPP_FUNCTION(5,	"au",		"i2slrclk"),
+		 MPP_FUNCTION(6,	"sdio",		"wr_protect"),
+		 MPP_FUNCTION(7,	"ge",		"mdc"),
+		 MPP_FUNCTION(9,	"pcie0",	"clkreq"),
+		 MPP_FUNCTION(10,	"mss_gpio2",	NULL)),
+	MPP_MODE(35,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sata1",	"present_act"),
+		 MPP_FUNCTION(2,	"i2c1",		"sda"),
+		 MPP_FUNCTION(3,	"mss_spi",	"clk"),
+		 MPP_FUNCTION(4,	"tdm",		"pclk"),
+		 MPP_FUNCTION(5,	"au",		"i2sdo_spdifo"),
+		 MPP_FUNCTION(6,	"sdio",		"card_detect"),
+		 MPP_FUNCTION(7,	"xg",		"mdio"),
+		 MPP_FUNCTION(8,	"ge",		"mdio"),
+		 MPP_FUNCTION(9,	"pcie",		"rstoutn"),
+		 MPP_FUNCTION(10,	"mss_gpio3",	NULL)),
+	MPP_MODE(36,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"synce2",	"clk"),
+		 MPP_FUNCTION(2,	"i2c1",		"sck"),
+		 MPP_FUNCTION(3,	"ptp",		"clk"),
+		 MPP_FUNCTION(4,	"synce1",	"clk"),
+		 MPP_FUNCTION(5,	"au",		"i2sbclk"),
+		 MPP_FUNCTION(6,	"sata0",	"present_act"),
+		 MPP_FUNCTION(7,	"xg",		"mdc"),
+		 MPP_FUNCTION(8,	"ge",		"mdc"),
+		 MPP_FUNCTION(9,	"pcie2",	"clkreq"),
+		 MPP_FUNCTION(10,	"mss_gpio5",	NULL)),
+	MPP_MODE(37,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"uart2",	"rxd"),
+		 MPP_FUNCTION(2,	"i2c0",		"sck"),
+		 MPP_FUNCTION(3,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(4,	"tdm",		"intn"),
+		 MPP_FUNCTION(5,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(6,	"sata1",	"present_act"),
+		 MPP_FUNCTION(7,	"ge",		"mdc"),
+		 MPP_FUNCTION(8,	"xg",		"mdc"),
+		 MPP_FUNCTION(9,	"pcie1",	"clkreq"),
+		 MPP_FUNCTION(10,	"mss_gpio6",	NULL),
+		 MPP_FUNCTION(11,	"link",		"rd_out_cp2cp")),
+	MPP_MODE(38,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"uart2",	"txd"),
+		 MPP_FUNCTION(2,	"i2c0",		"sda"),
+		 MPP_FUNCTION(3,	"ptp",		"pulse"),
+		 MPP_FUNCTION(4,	"tdm",		"rstn"),
+		 MPP_FUNCTION(5,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(6,	"sata0",	"present_act"),
+		 MPP_FUNCTION(7,	"ge",		"mdio"),
+		 MPP_FUNCTION(8,	"xg",		"mdio"),
+		 MPP_FUNCTION(9,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(10,	"mss_gpio7",	NULL),
+		 MPP_FUNCTION(11,	"ptp",		"pulse_cp2cp")),
+	MPP_MODE(39,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sdio",		"wr_protect"),
+		 MPP_FUNCTION(4,	"au",		"i2sbclk"),
+		 MPP_FUNCTION(5,	"ptp",		"clk"),
+		 MPP_FUNCTION(6,	"spi0",		"csn1"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"mss_gpio0",	NULL)),
+	MPP_MODE(40,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sdio",		"pwr11"),
+		 MPP_FUNCTION(2,	"synce1",	"clk"),
+		 MPP_FUNCTION(3,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(4,	"au",		"i2sdo_spdifo"),
+		 MPP_FUNCTION(5,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(6,	"spi0",		"clk"),
+		 MPP_FUNCTION(7,	"uart1",	"txd"),
+		 MPP_FUNCTION(8,	"ge",		"mdio"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"mss_gpio1",	NULL)),
+	MPP_MODE(41,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sdio",		"pwr10"),
+		 MPP_FUNCTION(2,	"sdio",		"bus_pwr"),
+		 MPP_FUNCTION(3,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(4,	"au",		"i2slrclk"),
+		 MPP_FUNCTION(5,	"ptp",		"pulse"),
+		 MPP_FUNCTION(6,	"spi0",		"mosi"),
+		 MPP_FUNCTION(7,	"uart1",	"rxd"),
+		 MPP_FUNCTION(8,	"ge",		"mdc"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"mss_gpio2",	NULL),
+		 MPP_FUNCTION(11,	"rei",		"out_cp2cp")),
+	MPP_MODE(42,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sdio",		"v18_en"),
+		 MPP_FUNCTION(2,	"sdio",		"wr_protect"),
+		 MPP_FUNCTION(3,	"synce2",	"clk"),
+		 MPP_FUNCTION(4,	"au",		"i2smclk"),
+		 MPP_FUNCTION(5,	"mss_uart",	"txd"),
+		 MPP_FUNCTION(6,	"spi0",		"miso"),
+		 MPP_FUNCTION(7,	"uart1",	"cts"),
+		 MPP_FUNCTION(8,	"xg",		"mdc"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"mss_gpio4",	NULL)),
+	MPP_MODE(43,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"sdio",		"card_detect"),
+		 MPP_FUNCTION(3,	"synce1",	"clk"),
+		 MPP_FUNCTION(4,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(5,	"mss_uart",	"rxd"),
+		 MPP_FUNCTION(6,	"spi0",		"csn0"),
+		 MPP_FUNCTION(7,	"uart1",	"rts"),
+		 MPP_FUNCTION(8,	"xg",		"mdio"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"mss_gpio5",	NULL),
+		 MPP_FUNCTION(11,	"wakeup",	"out_cp2cp")),
+	MPP_MODE(44,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txd2"),
+		 MPP_FUNCTION(7,	"uart0",	"rts"),
+		 MPP_FUNCTION(11,	"ptp",		"clk_cp2cp")),
+	MPP_MODE(45,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txd3"),
+		 MPP_FUNCTION(7,	"uart0",	"txd"),
+		 MPP_FUNCTION(9,	"pcie",		"rstoutn")),
+	MPP_MODE(46,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txd1"),
+		 MPP_FUNCTION(7,	"uart1",	"rts")),
+	MPP_MODE(47,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txd0"),
+		 MPP_FUNCTION(5,	"spi1",		"clk"),
+		 MPP_FUNCTION(7,	"uart1",	"txd"),
+		 MPP_FUNCTION(8,	"ge",		"mdc")),
+	MPP_MODE(48,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txctl_txen"),
+		 MPP_FUNCTION(5,	"spi1",		"mosi"),
+		 MPP_FUNCTION(8,	"xg",		"mdc"),
+		 MPP_FUNCTION(11,	"wakeup",	"in_cp2cp")),
+	MPP_MODE(49,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"txclkout"),
+		 MPP_FUNCTION(2,	"mii",		"crs"),
+		 MPP_FUNCTION(5,	"spi1",		"miso"),
+		 MPP_FUNCTION(7,	"uart1",	"rxd"),
+		 MPP_FUNCTION(8,	"ge",		"mdio"),
+		 MPP_FUNCTION(9,	"pcie0",	"clkreq"),
+		 MPP_FUNCTION(10,	"sdio",		"v18_en"),
+		 MPP_FUNCTION(11,	"sei",		"out_cp2cp")),
+	MPP_MODE(50,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxclk"),
+		 MPP_FUNCTION(2,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(5,	"spi1",		"csn0"),
+		 MPP_FUNCTION(6,	"uart2",	"txd"),
+		 MPP_FUNCTION(7,	"uart0",	"rxd"),
+		 MPP_FUNCTION(8,	"xg",		"mdio"),
+		 MPP_FUNCTION(10,	"sdio",		"pwr11")),
+	MPP_MODE(51,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxd0"),
+		 MPP_FUNCTION(2,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(5,	"spi1",		"csn1"),
+		 MPP_FUNCTION(6,	"uart2",	"rxd"),
+		 MPP_FUNCTION(7,	"uart0",	"cts"),
+		 MPP_FUNCTION(10,	"sdio",		"pwr10")),
+	MPP_MODE(52,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxd1"),
+		 MPP_FUNCTION(2,	"synce1",	"clk"),
+		 MPP_FUNCTION(4,	"synce2",	"clk"),
+		 MPP_FUNCTION(5,	"spi1",		"csn2"),
+		 MPP_FUNCTION(7,	"uart1",	"cts"),
+		 MPP_FUNCTION(8,	"led",		"clk"),
+		 MPP_FUNCTION(9,	"pcie",		"rstoutn"),
+		 MPP_FUNCTION(10,	"pcie0",	"clkreq")),
+	MPP_MODE(53,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxd2"),
+		 MPP_FUNCTION(3,	"ptp",		"clk"),
+		 MPP_FUNCTION(5,	"spi1",		"csn3"),
+		 MPP_FUNCTION(7,	"uart1",	"rxd"),
+		 MPP_FUNCTION(8,	"led",		"stb"),
+		 MPP_FUNCTION(11,	"sdio",		"led")),
+	MPP_MODE(54,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxd3"),
+		 MPP_FUNCTION(2,	"synce2",	"clk"),
+		 MPP_FUNCTION(3,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(4,	"synce1",	"clk"),
+		 MPP_FUNCTION(8,	"led",		"data"),
+		 MPP_FUNCTION(10,	"sdio",		"hw_rst"),
+		 MPP_FUNCTION(11,	"sdio",		"wr_protect")),
+	MPP_MODE(55,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"ge1",		"rxctl_rxdv"),
+		 MPP_FUNCTION(3,	"ptp",		"pulse"),
+		 MPP_FUNCTION(10,	"sdio",		"led"),
+		 MPP_FUNCTION(11,	"sdio",		"card_detect")),
+	MPP_MODE(56,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(4,	"tdm",		"drx"),
+		 MPP_FUNCTION(5,	"au",		"i2sdo_spdifo"),
+		 MPP_FUNCTION(6,	"spi0",		"clk"),
+		 MPP_FUNCTION(7,	"uart1",	"rxd"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(14,	"sdio",		"clk")),
+	MPP_MODE(57,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(2,	"mss_i2c",	"sda"),
+		 MPP_FUNCTION(3,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(4,	"tdm",		"intn"),
+		 MPP_FUNCTION(5,	"au",		"i2sbclk"),
+		 MPP_FUNCTION(6,	"spi0",		"mosi"),
+		 MPP_FUNCTION(7,	"uart1",	"txd"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(14,	"sdio",		"cmd")),
+	MPP_MODE(58,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(2,	"mss_i2c",	"sck"),
+		 MPP_FUNCTION(3,	"ptp",		"clk"),
+		 MPP_FUNCTION(4,	"tdm",		"rstn"),
+		 MPP_FUNCTION(5,	"au",		"i2sdi"),
+		 MPP_FUNCTION(6,	"spi0",		"miso"),
+		 MPP_FUNCTION(7,	"uart1",	"cts"),
+		 MPP_FUNCTION(8,	"led",		"clk"),
+		 MPP_FUNCTION(14,	"sdio",		"d0")),
+	MPP_MODE(59,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mss_gpio7",	NULL),
+		 MPP_FUNCTION(2,	"synce2",	"clk"),
+		 MPP_FUNCTION(4,	"tdm",		"fsync"),
+		 MPP_FUNCTION(5,	"au",		"i2slrclk"),
+		 MPP_FUNCTION(6,	"spi0",		"csn0"),
+		 MPP_FUNCTION(7,	"uart0",	"cts"),
+		 MPP_FUNCTION(8,	"led",		"stb"),
+		 MPP_FUNCTION(9,	"uart1",	"txd"),
+		 MPP_FUNCTION(14,	"sdio",		"d1")),
+	MPP_MODE(60,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mss_gpio6",	NULL),
+		 MPP_FUNCTION(3,	"ptp",		"pulse"),
+		 MPP_FUNCTION(4,	"tdm",		"dtx"),
+		 MPP_FUNCTION(5,	"au",		"i2smclk"),
+		 MPP_FUNCTION(6,	"spi0",		"csn1"),
+		 MPP_FUNCTION(7,	"uart0",	"rts"),
+		 MPP_FUNCTION(8,	"led",		"data"),
+		 MPP_FUNCTION(9,	"uart1",	"rxd"),
+		 MPP_FUNCTION(14,	"sdio",		"d2")),
+	MPP_MODE(61,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mss_gpio5",	NULL),
+		 MPP_FUNCTION(3,	"ptp",		"clk"),
+		 MPP_FUNCTION(4,	"tdm",		"pclk"),
+		 MPP_FUNCTION(5,	"au",		"i2sextclk"),
+		 MPP_FUNCTION(6,	"spi0",		"csn2"),
+		 MPP_FUNCTION(7,	"uart0",	"txd"),
+		 MPP_FUNCTION(8,	"uart2",	"txd"),
+		 MPP_FUNCTION(9,	"sata1",	"present_act"),
+		 MPP_FUNCTION(10,	"ge",		"mdio"),
+		 MPP_FUNCTION(14,	"sdio",		"d3")),
+	MPP_MODE(62,
+		 MPP_FUNCTION(0,	"gpio",		NULL),
+		 MPP_FUNCTION(1,	"mss_gpio4",	NULL),
+		 MPP_FUNCTION(2,	"synce1",	"clk"),
+		 MPP_FUNCTION(3,	"ptp",		"pclk_out"),
+		 MPP_FUNCTION(5,	"sata1",	"present_act"),
+		 MPP_FUNCTION(6,	"spi0",		"csn3"),
+		 MPP_FUNCTION(7,	"uart0",	"rxd"),
+		 MPP_FUNCTION(8,	"uart2",	"rxd"),
+		 MPP_FUNCTION(9,	"sata0",	"present_act"),
+		 MPP_FUNCTION(10,	"ge",		"mdc")),
+};
+
+static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
+	{
+		.compatible	= "marvell,armada-7k-pinctrl",
+		.data		= (void *) V_ARMADA_7K,
+	},
+	{
+		.compatible	= "marvell,armada-8k-cpm-pinctrl",
+		.data		= (void *) V_ARMADA_8K_CPM,
+	},
+	{
+		.compatible	= "marvell,armada-8k-cps-pinctrl",
+		.data		= (void *) V_ARMADA_8K_CPS,
+	},
+	{ },
+};
+
+static const struct mvebu_mpp_ctrl armada_cp110_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 62, NULL, mvebu_regmap_mpp_ctrl),
+};
+
+static void mvebu_pinctrl_assign_variant(struct mvebu_mpp_mode *m,
+					 u8 variant)
+{
+	struct mvebu_mpp_ctrl_setting *s;
+
+	for (s = m->settings ; s->name ; s++)
+		s->variant = variant;
+}
+
+static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc;
+	const struct of_device_id *match =
+		of_match_device(armada_cp110_pinctrl_of_match, &pdev->dev);
+	int i;
+
+	if (!pdev->dev.parent)
+		return -ENODEV;
+
+	soc = devm_kzalloc(&pdev->dev,
+			   sizeof(struct mvebu_pinctrl_soc_info), GFP_KERNEL);
+	if (!soc)
+		return -ENOMEM;
+
+	soc->variant = (unsigned long) match->data & 0xff;
+	soc->controls = armada_cp110_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(armada_cp110_mpp_controls);
+	soc->modes = armada_cp110_mpp_modes;
+	soc->nmodes = ARRAY_SIZE(armada_cp110_mpp_modes);
+	for (i = 0; i < ARRAY_SIZE(armada_cp110_mpp_modes); i++) {
+		struct mvebu_mpp_mode *m = &armada_cp110_mpp_modes[i];
+
+		switch (i) {
+		case 0 ... 31:
+			mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS);
+			break;
+		case 32 ... 38:
+			mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+			break;
+		case 39 ... 43:
+			mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM);
+			break;
+		case 44 ... 62:
+			mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+			break;
+		}
+	}
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
+}
+
+static struct platform_driver armada_cp110_pinctrl_driver = {
+	.driver = {
+		.name = "armada-cp110-pinctrl",
+		.of_match_table = of_match_ptr(armada_cp110_pinctrl_of_match),
+	},
+	.probe = armada_cp110_pinctrl_probe,
+};
+
+builtin_platform_driver(armada_cp110_pinctrl_driver);
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (5 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-20 14:34   ` Gregory CLEMENT
  2017-06-12 15:34 ` [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs Gregory CLEMENT
  2017-06-12 15:35 ` [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K Gregory CLEMENT
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.

The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.

These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-7020.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-7040.dtsi  |  2 +-
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi  | 53 ++++++++++++++++++-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-8040.dtsi  |  3 +-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 60 ++++++++++++++++++++-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi |  4 +-
 7 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi

diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
 	model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
  */
 
 #include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
 
 / {
 	model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index 000000000000..f6c22665d091
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+&cpm_syscon0 {
+	cpm_pinctrl: pinctrl {
+		compatible = "marvell,armada-7k-pinctrl";
+	};
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
  */
 
 #include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
 
 / {
 	model = "Marvell Armada 8020";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 33813a75bc30..60fe84f5cbcc 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -46,8 +46,7 @@
  */
 
 #include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
 
 / {
 	model = "Marvell Armada 8040";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
new file mode 100644
index 000000000000..93d1de03b39a
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 80x0 SoC family
+ */
+
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+&cpm_syscon0 {
+	cpm_pinctrl: pinctrl {
+		compatible = "marvell,armada-8k-cpm-pinctrl";
+	};
+};
+
+&cps_syscon0 {
+	cps_pinctrl: pinctrl {
+		compatible = "marvell,armada-8k-cps-pinctrl";
+	};
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 205037e3e7dc..4a1b6e0a604a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -248,6 +248,10 @@
 					compatible = "marvell,ap806-clock";
 					#clock-cells = <1>;
 				};
+
+				ap_pinctrl: pinctrl {
+					compatible = "marvell,ap806-pinctrl";
+				};
 			};
 		};
 	};
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (6 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K Gregory CLEMENT
@ 2017-06-12 15:34 ` Gregory CLEMENT
  2017-06-16  9:29   ` Linus Walleij
  2017-06-12 15:35 ` [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K Gregory CLEMENT
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:34 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

The Armada 7K and 8K SoCs use the same gpio controller as most of the
other mvebu SoCs. However, the main difference is that the GPIO
controller is part of a bigger system controller, and a syscon is used to
control the overall system controller. Therefore, the driver needs to be
adjusted to retrieve the regmap of the syscon to access registers, and
account for the fact that registers are located at a certain offset
within the regmap.

This commit add the support of the syscon and introduce a new variant for
this case.

It was based on the preliminary work of Thomas Petazzoni.

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/gpio/gpio-mvebu.c | 212 +++++++++++++++++++++++++--------------
 1 file changed, 141 insertions(+), 71 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index d5939913d310..463e4f26743c 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,6 +42,7 @@
 #include <linux/irq.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/pinctrl/consumer.h>
@@ -88,6 +89,7 @@
 #define MVEBU_GPIO_SOC_VARIANT_ORION	0x1
 #define MVEBU_GPIO_SOC_VARIANT_MV78200	0x2
 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+#define MVEBU_GPIO_SOC_VARIANT_A8K	0x4
 
 #define MVEBU_MAX_GPIO_PER_BANK		32
 
@@ -108,6 +110,7 @@ struct mvebu_pwm {
 struct mvebu_gpio_chip {
 	struct gpio_chip   chip;
 	struct regmap     *regs;
+	u32		   offset;
 	struct regmap     *percpu_regs;
 	int		   irqbase;
 	struct irq_domain *domain;
@@ -139,8 +142,9 @@ static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
 	switch (mvchip->soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
 		*map = mvchip->regs;
-		*offset = GPIO_EDGE_CAUSE_OFF;
+		*offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 		cpu = smp_processor_id();
@@ -183,8 +187,9 @@ mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
 
 	switch (mvchip->soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
 		*map = mvchip->regs;
-		*offset = GPIO_EDGE_MASK_OFF;
+		*offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 		cpu = smp_processor_id();
@@ -232,8 +237,9 @@ mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
 
 	switch (mvchip->soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
 		*map = mvchip->regs;
-		*offset = GPIO_LEVEL_MASK_OFF;
+		*offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 		cpu = smp_processor_id();
@@ -294,7 +300,7 @@ static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
 {
 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-	regmap_update_bits(mvchip->regs, GPIO_OUT_OFF,
+	regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
 			   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -303,16 +309,18 @@ static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 	u32 u;
 
-	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
+	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
 
 	if (u & BIT(pin)) {
 		u32 data_in, in_pol;
 
-		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
-		regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
+		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
+			    &data_in);
+		regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+			    &in_pol);
 		u = data_in ^ in_pol;
 	} else {
-		regmap_read(mvchip->regs, GPIO_OUT_OFF, &u);
+		regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
 	}
 
 	return (u >> pin) & 1;
@@ -323,7 +331,7 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
 {
 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 
-	regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF,
+	regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
 			   BIT(pin), value ? BIT(pin) : 0);
 }
 
@@ -340,7 +348,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
 	if (ret)
 		return ret;
 
-	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
+	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
 			   BIT(pin), BIT(pin));
 
 	return 0;
@@ -363,7 +371,7 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
 	mvebu_gpio_blink(chip, pin, 0);
 	mvebu_gpio_set(chip, pin, value);
 
-	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
+	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
 			   BIT(pin), 0);
 
 	return 0;
@@ -478,7 +486,7 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 
 	pin = d->hwirq;
 
-	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
+	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
 	if ((u & BIT(pin)) == 0)
 		return -EINVAL;
 
@@ -497,19 +505,23 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 	case IRQ_TYPE_LEVEL_HIGH:
-		regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
+		regmap_update_bits(mvchip->regs,
+				   GPIO_IN_POL_OFF + mvchip->offset,
 				   BIT(pin), 0);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
 	case IRQ_TYPE_LEVEL_LOW:
-		regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
+		regmap_update_bits(mvchip->regs,
+				   GPIO_IN_POL_OFF + mvchip->offset,
 				   BIT(pin), BIT(pin));
 		break;
 	case IRQ_TYPE_EDGE_BOTH: {
 		u32 data_in, in_pol, val;
 
-		regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
-		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
+		regmap_read(mvchip->regs,
+			    GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
+		regmap_read(mvchip->regs,
+			    GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 
 		/*
 		 * set initial polarity based on current input level
@@ -519,7 +531,8 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 		else
 			val = 0; /* raising */
 
-		regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
+		regmap_update_bits(mvchip->regs,
+				   GPIO_IN_POL_OFF + mvchip->offset,
 				   BIT(pin), val);
 		break;
 	}
@@ -539,7 +552,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
 
 	chained_irq_enter(chip, desc);
 
-	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
+	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 	level_mask = mvebu_gpio_read_level_mask(mvchip);
 	edge_cause = mvebu_gpio_read_edge_cause(mvchip);
 	edge_mask  = mvebu_gpio_read_edge_mask(mvchip);
@@ -559,9 +572,13 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
 			/* Swap polarity (race with GPIO line) */
 			u32 polarity;
 
-			regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &polarity);
+			regmap_read(mvchip->regs,
+				    GPIO_IN_POL_OFF + mvchip->offset,
+				    &polarity);
 			polarity ^= BIT(i);
-			regmap_write(mvchip->regs, GPIO_IN_POL_OFF, polarity);
+			regmap_write(mvchip->regs,
+				     GPIO_IN_POL_OFF + mvchip->offset,
+				     polarity);
 		}
 
 		generic_handle_irq(irq);
@@ -664,7 +681,7 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
 			state->period = 1;
 	}
 
-	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &u);
+	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
 	if (u)
 		state->enabled = true;
 	else
@@ -727,7 +744,7 @@ static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
 {
 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
 
-	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
+	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
 		    &mvpwm->blink_select);
 	mvpwm->blink_on_duration =
 		readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
@@ -739,7 +756,7 @@ static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
 {
 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
 
-	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
+	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
 		     mvpwm->blink_select);
 	writel_relaxed(mvpwm->blink_on_duration,
 		       mvebu_pwmreg_blink_on_duration(mvpwm));
@@ -783,7 +800,8 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
 		set = U32_MAX;
 	else
 		return -EINVAL;
-	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, 0);
+	regmap_write(mvchip->regs,
+		     GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 0);
 
 	mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
 	if (!mvpwm)
@@ -826,11 +844,11 @@ static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
 	int i;
 
-	regmap_read(mvchip->regs, GPIO_OUT_OFF, &out);
-	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &io_conf);
-	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &blink);
-	regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
-	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
+	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
+	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
+	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
+	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
+	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 	cause	= mvebu_gpio_read_edge_cause(mvchip);
 	edg_msk	= mvebu_gpio_read_edge_mask(mvchip);
 	lvl_msk	= mvebu_gpio_read_level_mask(mvchip);
@@ -892,6 +910,10 @@ static const struct of_device_id mvebu_gpio_of_match[] = {
 		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
 	},
 	{
+		.compatible = "marvell,armada-8k-gpio",
+		.data       = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
+	},
+	{
 		/* sentinel */
 	},
 };
@@ -901,16 +923,21 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
 	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
 	int i;
 
-	regmap_read(mvchip->regs, GPIO_OUT_OFF, &mvchip->out_reg);
-	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &mvchip->io_conf_reg);
-	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &mvchip->blink_en_reg);
-	regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &mvchip->in_pol_reg);
+	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
+		    &mvchip->out_reg);
+	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+		    &mvchip->io_conf_reg);
+	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+		    &mvchip->blink_en_reg);
+	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+		    &mvchip->in_pol_reg);
 
 	switch (mvchip->soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
-		regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF,
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
+		regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
 			    &mvchip->edge_mask_regs[0]);
-		regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF,
+		regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
 			    &mvchip->level_mask_regs[0]);
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
@@ -948,16 +975,21 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
 	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
 	int i;
 
-	regmap_write(mvchip->regs, GPIO_OUT_OFF, mvchip->out_reg);
-	regmap_write(mvchip->regs, GPIO_IO_CONF_OFF, mvchip->io_conf_reg);
-	regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF, mvchip->blink_en_reg);
-	regmap_write(mvchip->regs, GPIO_IN_POL_OFF, mvchip->in_pol_reg);
+	regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
+		     mvchip->out_reg);
+	regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+		     mvchip->io_conf_reg);
+	regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+		     mvchip->blink_en_reg);
+	regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+		     mvchip->in_pol_reg);
 
 	switch (mvchip->soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
-		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF,
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
+		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
 			     mvchip->edge_mask_regs[0]);
-		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF,
+		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
 			     mvchip->level_mask_regs[0]);
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
@@ -997,15 +1029,68 @@ static const struct regmap_config mvebu_gpio_regmap_config = {
 	.fast_io = true,
 };
 
+static int mvebu_gpio_probe_raw(struct platform_device *pdev,
+				struct mvebu_gpio_chip *mvchip)
+{
+	struct resource *res;
+	void __iomem *base;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
+					     &mvebu_gpio_regmap_config);
+	if (IS_ERR(mvchip->regs))
+		return PTR_ERR(mvchip->regs);
+
+	/*
+	 * For the legacy SoCs, the regmap directly maps to the GPIO
+	 * registers, so no offset is needed.
+	 */
+	mvchip->offset = 0;
+
+	/*
+	 * The Armada XP has a second range of registers for the
+	 * per-CPU registers
+	 */
+	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		base = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(base))
+			return PTR_ERR(base);
+
+		mvchip->percpu_regs =
+			devm_regmap_init_mmio(&pdev->dev, base,
+					      &mvebu_gpio_regmap_config);
+		if (IS_ERR(mvchip->percpu_regs))
+			return PTR_ERR(mvchip->percpu_regs);
+	}
+
+	return 0;
+}
+
+static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
+				   struct mvebu_gpio_chip *mvchip)
+{
+	mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
+	if (IS_ERR(mvchip->regs))
+		return PTR_ERR(mvchip->regs);
+
+	if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
+		return -EINVAL;
+
+	return 0;
+}
+
 static int mvebu_gpio_probe(struct platform_device *pdev)
 {
 	struct mvebu_gpio_chip *mvchip;
 	const struct of_device_id *match;
 	struct device_node *np = pdev->dev.of_node;
-	struct resource *res;
 	struct irq_chip_generic *gc;
 	struct irq_chip_type *ct;
-	void __iomem *base;
 	unsigned int ngpios;
 	bool have_irqs;
 	int soc_variant;
@@ -1061,41 +1146,26 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
 	mvchip->chip.of_node = np;
 	mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
-
-	mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
-					     &mvebu_gpio_regmap_config);
-	if (IS_ERR(mvchip->regs))
-		return PTR_ERR(mvchip->regs);
+	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
+		err = mvebu_gpio_probe_syscon(pdev, mvchip);
+	else
+		err = mvebu_gpio_probe_raw(pdev, mvchip);
 
-	/*
-	 * The Armada XP has a second range of registers for the
-	 * per-CPU registers
-	 */
-	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-		base = devm_ioremap_resource(&pdev->dev, res);
-		if (IS_ERR(base))
-			return PTR_ERR(base);
-
-		mvchip->percpu_regs =
-			devm_regmap_init_mmio(&pdev->dev, base,
-					      &mvebu_gpio_regmap_config);
-		if (IS_ERR(mvchip->percpu_regs))
-			return PTR_ERR(mvchip->percpu_regs);
-	}
+	if (err)
+		return err;
 
 	/*
 	 * Mask and clear GPIO interrupts.
 	 */
 	switch (soc_variant) {
 	case MVEBU_GPIO_SOC_VARIANT_ORION:
-		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
-		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
-		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
+	case MVEBU_GPIO_SOC_VARIANT_A8K:
+		regmap_write(mvchip->regs,
+			     GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
+		regmap_write(mvchip->regs,
+			     GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
+		regmap_write(mvchip->regs,
+			     GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K
  2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
                   ` (7 preceding siblings ...)
  2017-06-12 15:34 ` [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs Gregory CLEMENT
@ 2017-06-12 15:35 ` Gregory CLEMENT
  2017-06-20 14:34   ` Gregory CLEMENT
  8 siblings, 1 reply; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-12 15:35 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel, Rob Herring,
	devicetree, Russell King, Nadav Haklai, Kostya Porotchkin,
	Neta Zur Hershkovits, Marcin Wojtas, Omri Itach, Shadi Ammouri

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.

The Armada 8K has two CP110 blocks, each having two GPIO controllers.
However, in each CP110 block, one of the GPIO controller cannot be
used: in the master CP110, only the second GPIO controller can be used,
while on the slave CP110, only the first GPIO controller can be used.

On the other side, the Armada 7K has only one CP110, but both its GPIO
controllers can be used.

For this reason, the GPIO controllers are marked as "disabled" in the
armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
enabled in the per-SoC dtsi files.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi         | 15 +++++++++-
 arch/arm64/boot/dts/marvell/armada-80x0.dtsi         | 16 +++++++++-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 10 ++++++-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 21 ++++++++++++-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 22 +++++++++++++-
 5 files changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index f6c22665d091..860b6ae9dcc5 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -46,6 +46,21 @@
 
 #include "armada-cp110-master.dtsi"
 
+/ {
+	aliases {
+		gpio1 = &cpm_gpio1;
+		gpio2 = &cpm_gpio2;
+	};
+};
+
+&cpm_gpio1 {
+	status = "okay";
+};
+
+&cpm_gpio2 {
+	status = "okay";
+};
+
 &cpm_syscon0 {
 	cpm_pinctrl: pinctrl {
 		compatible = "marvell,armada-7k-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 93d1de03b39a..666ebe96ba0d 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -47,6 +47,22 @@
 #include "armada-cp110-master.dtsi"
 #include "armada-cp110-slave.dtsi"
 
+/ {
+	aliases {
+		gpio1 = &cps_gpio1;
+		gpio2 = &cpm_gpio2;
+	};
+};
+
+/* The 80x0 has two CP blocks, but uses only one block from each. */
+&cps_gpio1 {
+	status = "okay";
+};
+
+&cpm_gpio2 {
+	status = "okay";
+};
+
 &cpm_syscon0 {
 	cpm_pinctrl: pinctrl {
 		compatible = "marvell,armada-8k-cpm-pinctrl";
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 4a1b6e0a604a..64608658de5a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -57,6 +57,7 @@
 	aliases {
 		serial0 = &uart0;
 		serial1 = &uart1;
+		gpio0 = &ap_gpio;
 	};
 
 	psci {
@@ -252,6 +253,15 @@
 				ap_pinctrl: pinctrl {
 					compatible = "marvell,ap806-pinctrl";
 				};
+
+				ap_gpio: gpio {
+					compatible = "marvell,armada-8k-gpio";
+					offset = <0x1040>;
+					ngpios = <19>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&ap_pinctrl 0 0 19>;
+				};
 			};
 		};
 	};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 96a4ff75b3b0..f88618185d58 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -104,6 +104,27 @@
 					compatible = "marvell,cp110-clock";
 					#clock-cells = <2>;
 				};
+
+				cpm_gpio1: gpio@100 {
+					compatible = "marvell,armada-8k-gpio";
+					offset = <0x100>;
+					ngpios = <32>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&cpm_pinctrl 0 0 32>;
+					status = "disabled";
+
+				};
+
+				cpm_gpio2: gpio@140 {
+					compatible = "marvell,armada-8k-gpio";
+					offset = <0x140>;
+					ngpios = <31>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&cpm_pinctrl 0 32 31>;
+					status = "disabled";
+				};
 			};
 
 			cpm_rtc: rtc@284000 {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 48a658aa5b32..f3a6e6742442 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -111,6 +111,28 @@
 					compatible = "marvell,cp110-clock";
 					#clock-cells = <2>;
 				};
+
+				cps_gpio1: gpio@100 {
+					compatible = "marvell,armada-8k-gpio";
+					offset = <0x100>;
+					ngpios = <32>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&cps_pinctrl 0 0 32>;
+					status = "disabled";
+
+				};
+
+				cps_gpio2: gpio@140 {
+					compatible = "marvell,armada-8k-gpio";
+					offset = <0x140>;
+					ngpios = <31>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&cps_pinctrl 0 32 31>;
+					status = "disabled";
+				};
+
 			};
 
 			cps_sata0: sata@540000 {
-- 
git-series 0.9.1

^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage
  2017-06-12 15:34 ` [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage Gregory CLEMENT
@ 2017-06-16  9:18   ` Linus Walleij
  0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:18 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri, Chris Packham, Ralph Sennhauser

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> In some place in the driver regmap_update_bits was misused. Indeed the
> last argument is not the value of the bit (or group of bits) itself but
> the mask value inside the register.
>
> So when setting the bit N, then the value must be BIT(N) and not 1.
>
> CC: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
> CC: Ralph Sennhauser <ralph.sennhauser@gmail.com>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Tested-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
> Tested-by: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Already applied this patch, sorry for missing the resend in the series.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap
  2017-06-12 15:34 ` [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap Gregory CLEMENT
@ 2017-06-16  9:20   ` Linus Walleij
  0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:20 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> The offset property of the pinctrl node, when a regmap is used in the
> device tree, was never used nor documented in the binding. Moreover, the
> compatible string is enough to let the driver know which offset using.
>
> So this patch removes the property and move the information at the driver
> level.
>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency
  2017-06-12 15:34 ` [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency Gregory CLEMENT
@ 2017-06-16  9:21   ` Linus Walleij
  0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:21 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Russell King <rmk+kernel@armlinux.org.uk>
>
> Armada 8040 also needs orion pinctrl, and as these symbols are only
> selected, there's no need to make them depend on PLAT_ORION.
>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver
  2017-06-12 15:34 ` [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver Gregory CLEMENT
@ 2017-06-16  9:22   ` Linus Walleij
  2017-06-21 12:53     ` Gregory CLEMENT
  0 siblings, 1 reply; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:22 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> This commit makes sure the drivers for the Armada 7K/8K pin controllers
> are enabled.
>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Please merge this through ARM SoC.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl
  2017-06-12 15:34 ` [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl Gregory CLEMENT
@ 2017-06-16  9:23   ` Linus Walleij
  0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:23 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri, Hanna Hawa

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Hanna Hawa <hannah@marvell.com>
>
> This commit adds a pinctrl driver for the pin-muxing controller found in
> the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
> interface is compatible with the one used by previous mvebu pin
> controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
> is used.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Reviewed-by: Shadi Ammouri <shadi@marvell.com>
> [updated for mvebu pinctrl changes
>  - converted to simple_mmio
>  - removed unimplemented .remove function
>  - removed DTS description
>   - converted  to use syscon/regmap
>  --rmk]
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl
  2017-06-12 15:34 ` [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl Gregory CLEMENT
@ 2017-06-16  9:24   ` Linus Walleij
  2017-06-16  9:26   ` Linus Walleij
  1 sibling, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:24 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri, Hanna Hawa, Grzegorz Jaszczyk

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Hanna Hawa <hannah@marvell.com>
>
> This commit adds a pinctrl driver for the CP110 part of the Marvell
> Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
> the MPP pins are available. On the other side, the Armada 8K has two
> CP110, and the available MPPs are split between the master CP110 (MPPs 32
> to 62) and the slave CP110 (MPPs 0 to 31).
>
> The register interface to control the MPPs is however the same as all
> other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Reviewed-by: Shadi Ammouri <shadi@marvell.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl
  2017-06-12 15:34 ` [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl Gregory CLEMENT
  2017-06-16  9:24   ` Linus Walleij
@ 2017-06-16  9:26   ` Linus Walleij
  1 sibling, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:26 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri, Hanna Hawa, Grzegorz Jaszczyk

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Hanna Hawa <hannah@marvell.com>
>
> This commit adds a pinctrl driver for the CP110 part of the Marvell
> Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
> the MPP pins are available. On the other side, the Armada 8K has two
> CP110, and the available MPPs are split between the master CP110 (MPPs 32
> to 62) and the slave CP110 (MPPs 0 to 31).
>
> The register interface to control the MPPs is however the same as all
> other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Reviewed-by: Shadi Ammouri <shadi@marvell.com>
>
> [updated for mvebu pinctrl and 4.9 changes:
>  - converted to simple_mmio
>  - converted to syscon/regmap
>  - removed unimplemented .remove function
>  - dropped DTS changes
>  - defered gpio ranges to DT
>  - fixed warning
>  - properly set soc->nmodes
>  -- rmk]
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> [ add missing MPP[61:56] function 14 (SDIO)
> -- Konstantin Porotchkin]
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
>
> [ allow to properly register more then one instance of this driver
> -- Grzegorz Jaszczyk]
> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
>
> [ - rebased on 4.12-rc1
>   - fixed the 80 character limit for mvebu_mpp_mode array
>   - aligned the compatible name on the ones already used
>   - fixed the MPP table for CP110: some MPP are not available on Armada 7K
> -- Gregory CLEMENT]
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs
  2017-06-12 15:34 ` [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs Gregory CLEMENT
@ 2017-06-16  9:29   ` Linus Walleij
  0 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2017-06-16  9:29 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri

On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> The Armada 7K and 8K SoCs use the same gpio controller as most of the
> other mvebu SoCs. However, the main difference is that the GPIO
> controller is part of a bigger system controller, and a syscon is used to
> control the overall system controller. Therefore, the driver needs to be
> adjusted to retrieve the regmap of the syscon to access registers, and
> account for the fact that registers are located at a certain offset
> within the regmap.
>
> This commit add the support of the syscon and introduce a new variant for
> this case.
>
> It was based on the preliminary work of Thomas Petazzoni.
>
> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  2017-06-12 15:34 ` [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K Gregory CLEMENT
@ 2017-06-20 14:34   ` Gregory CLEMENT
  0 siblings, 0 replies; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-20 14:34 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-gpio, linux-kernel, Thomas Petazzoni, Andrew Lunn,
	Jason Cooper, devicetree, Omri Itach, Nadav Haklai,
	Kostya Porotchkin, Russell King, Rob Herring,
	Neta Zur Hershkovits, Shadi Ammouri, Marcin Wojtas,
	linux-arm-kernel, Sebastian Hesselbarth

Hi,
 
 On lun., juin 12 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:

> Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
>
> The CP master being different between Armada 7k and Armada 8k. This
> commit introduces the intermediates files armada-70x0.dtsi and
> armada-80x0.dtsi.
>
> These new files will provide different compatible strings depending of
> the SoC family. They will also be the location for the pinmux
> configuration at the SoC level.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
>  arch/arm64/boot/dts/marvell/armada-7020.dtsi  |  2 +-
>  arch/arm64/boot/dts/marvell/armada-7040.dtsi  |  2 +-
>  arch/arm64/boot/dts/marvell/armada-70x0.dtsi  | 53 ++++++++++++++++++-
>  arch/arm64/boot/dts/marvell/armada-8020.dtsi  |  3 +-
>  arch/arm64/boot/dts/marvell/armada-8040.dtsi  |  3 +-
>  arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 60 ++++++++++++++++++++-
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi |  4 +-
>  7 files changed, 121 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
>  create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
> index 975e73302753..4ab012991d9d 100644
> --- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
> @@ -46,7 +46,7 @@
>   */
>  
>  #include "armada-ap806-dual.dtsi"
> -#include "armada-cp110-master.dtsi"
> +#include "armada-70x0.dtsi"
>  
>  / {
>  	model = "Marvell Armada 7020";
> diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> index 78d995d62707..cbe460b8fc00 100644
> --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> @@ -46,7 +46,7 @@
>   */
>  
>  #include "armada-ap806-quad.dtsi"
> -#include "armada-cp110-master.dtsi"
> +#include "armada-70x0.dtsi"
>  
>  / {
>  	model = "Marvell Armada 7040";
> diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> new file mode 100644
> index 000000000000..f6c22665d091
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> @@ -0,0 +1,53 @@
> +/*
> + * Copyright (C) 2017 Marvell Technology Group Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * Device Tree file for the Armada 70x0 SoC
> + */
> +
> +#include "armada-cp110-master.dtsi"
> +
> +&cpm_syscon0 {
> +	cpm_pinctrl: pinctrl {
> +		compatible = "marvell,armada-7k-pinctrl";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
> index 7c08f1f28d9e..0ba0bc942598 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
> @@ -46,8 +46,7 @@
>   */
>  
>  #include "armada-ap806-dual.dtsi"
> -#include "armada-cp110-master.dtsi"
> -#include "armada-cp110-slave.dtsi"
> +#include "armada-80x0.dtsi"
>  
>  / {
>  	model = "Marvell Armada 8020";
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> index 33813a75bc30..60fe84f5cbcc 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> @@ -46,8 +46,7 @@
>   */
>  
>  #include "armada-ap806-quad.dtsi"
> -#include "armada-cp110-master.dtsi"
> -#include "armada-cp110-slave.dtsi"
> +#include "armada-80x0.dtsi"
>  
>  / {
>  	model = "Marvell Armada 8040";
> diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> new file mode 100644
> index 000000000000..93d1de03b39a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> @@ -0,0 +1,60 @@
> +/*
> + * Copyright (C) 2017 Marvell Technology Group Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * Device Tree file for the Armada 80x0 SoC family
> + */
> +
> +#include "armada-cp110-master.dtsi"
> +#include "armada-cp110-slave.dtsi"
> +
> +&cpm_syscon0 {
> +	cpm_pinctrl: pinctrl {
> +		compatible = "marvell,armada-8k-cpm-pinctrl";
> +	};
> +};
> +
> +&cps_syscon0 {
> +	cps_pinctrl: pinctrl {
> +		compatible = "marvell,armada-8k-cps-pinctrl";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index 205037e3e7dc..4a1b6e0a604a 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -248,6 +248,10 @@
>  					compatible = "marvell,ap806-clock";
>  					#clock-cells = <1>;
>  				};
> +
> +				ap_pinctrl: pinctrl {
> +					compatible = "marvell,ap806-pinctrl";
> +				};
>  			};
>  		};
>  	};
> -- 
> git-series 0.9.1
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K
  2017-06-12 15:35 ` [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K Gregory CLEMENT
@ 2017-06-20 14:34   ` Gregory CLEMENT
  0 siblings, 0 replies; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-20 14:34 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-gpio, linux-kernel, Thomas Petazzoni, Andrew Lunn,
	Jason Cooper, devicetree, Omri Itach, Nadav Haklai,
	Kostya Porotchkin, Russell King, Rob Herring,
	Neta Zur Hershkovits, Shadi Ammouri, Marcin Wojtas,
	linux-arm-kernel, Sebastian Hesselbarth

Hi,
 
 On lun., juin 12 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:

> Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
>
> The Armada 8K has two CP110 blocks, each having two GPIO controllers.
> However, in each CP110 block, one of the GPIO controller cannot be
> used: in the master CP110, only the second GPIO controller can be used,
> while on the slave CP110, only the first GPIO controller can be used.
>
> On the other side, the Armada 7K has only one CP110, but both its GPIO
> controllers can be used.
>
> For this reason, the GPIO controllers are marked as "disabled" in the
> armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
> enabled in the per-SoC dtsi files.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
>  arch/arm64/boot/dts/marvell/armada-70x0.dtsi         | 15 +++++++++-
>  arch/arm64/boot/dts/marvell/armada-80x0.dtsi         | 16 +++++++++-
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 10 ++++++-
>  arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 21 ++++++++++++-
>  arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 22 +++++++++++++-
>  5 files changed, 84 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> index f6c22665d091..860b6ae9dcc5 100644
> --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> @@ -46,6 +46,21 @@
>  
>  #include "armada-cp110-master.dtsi"
>  
> +/ {
> +	aliases {
> +		gpio1 = &cpm_gpio1;
> +		gpio2 = &cpm_gpio2;
> +	};
> +};
> +
> +&cpm_gpio1 {
> +	status = "okay";
> +};
> +
> +&cpm_gpio2 {
> +	status = "okay";
> +};
> +
>  &cpm_syscon0 {
>  	cpm_pinctrl: pinctrl {
>  		compatible = "marvell,armada-7k-pinctrl";
> diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> index 93d1de03b39a..666ebe96ba0d 100644
> --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> @@ -47,6 +47,22 @@
>  #include "armada-cp110-master.dtsi"
>  #include "armada-cp110-slave.dtsi"
>  
> +/ {
> +	aliases {
> +		gpio1 = &cps_gpio1;
> +		gpio2 = &cpm_gpio2;
> +	};
> +};
> +
> +/* The 80x0 has two CP blocks, but uses only one block from each. */
> +&cps_gpio1 {
> +	status = "okay";
> +};
> +
> +&cpm_gpio2 {
> +	status = "okay";
> +};
> +
>  &cpm_syscon0 {
>  	cpm_pinctrl: pinctrl {
>  		compatible = "marvell,armada-8k-cpm-pinctrl";
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index 4a1b6e0a604a..64608658de5a 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -57,6 +57,7 @@
>  	aliases {
>  		serial0 = &uart0;
>  		serial1 = &uart1;
> +		gpio0 = &ap_gpio;
>  	};
>  
>  	psci {
> @@ -252,6 +253,15 @@
>  				ap_pinctrl: pinctrl {
>  					compatible = "marvell,ap806-pinctrl";
>  				};
> +
> +				ap_gpio: gpio {
> +					compatible = "marvell,armada-8k-gpio";
> +					offset = <0x1040>;
> +					ngpios = <19>;
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					gpio-ranges = <&ap_pinctrl 0 0 19>;
> +				};
>  			};
>  		};
>  	};
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index 96a4ff75b3b0..f88618185d58 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -104,6 +104,27 @@
>  					compatible = "marvell,cp110-clock";
>  					#clock-cells = <2>;
>  				};
> +
> +				cpm_gpio1: gpio@100 {
> +					compatible = "marvell,armada-8k-gpio";
> +					offset = <0x100>;
> +					ngpios = <32>;
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					gpio-ranges = <&cpm_pinctrl 0 0 32>;
> +					status = "disabled";
> +
> +				};
> +
> +				cpm_gpio2: gpio@140 {
> +					compatible = "marvell,armada-8k-gpio";
> +					offset = <0x140>;
> +					ngpios = <31>;
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					gpio-ranges = <&cpm_pinctrl 0 32 31>;
> +					status = "disabled";
> +				};
>  			};
>  
>  			cpm_rtc: rtc@284000 {
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index 48a658aa5b32..f3a6e6742442 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -111,6 +111,28 @@
>  					compatible = "marvell,cp110-clock";
>  					#clock-cells = <2>;
>  				};
> +
> +				cps_gpio1: gpio@100 {
> +					compatible = "marvell,armada-8k-gpio";
> +					offset = <0x100>;
> +					ngpios = <32>;
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					gpio-ranges = <&cps_pinctrl 0 0 32>;
> +					status = "disabled";
> +
> +				};
> +
> +				cps_gpio2: gpio@140 {
> +					compatible = "marvell,armada-8k-gpio";
> +					offset = <0x140>;
> +					ngpios = <31>;
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					gpio-ranges = <&cps_pinctrl 0 32 31>;
> +					status = "disabled";
> +				};
> +
>  			};
>  
>  			cps_sata0: sata@540000 {
> -- 
> git-series 0.9.1
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

^ permalink raw reply	[flat|nested] 21+ messages in thread

* Re: [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver
  2017-06-16  9:22   ` Linus Walleij
@ 2017-06-21 12:53     ` Gregory CLEMENT
  0 siblings, 0 replies; 21+ messages in thread
From: Gregory CLEMENT @ 2017-06-21 12:53 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-gpio, linux-kernel, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Rob Herring, devicetree, Russell King, Nadav Haklai,
	Kostya Porotchkin, Neta Zur Hershkovits, Marcin Wojtas,
	Omri Itach, Shadi Ammouri

Hi Linus,
 
 On ven., juin 16 2017, Linus Walleij <linus.walleij@linaro.org> wrote:

> On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>
>> This commit makes sure the drivers for the Armada 7K/8K pin controllers
>> are enabled.
>>
>> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Please merge this through ARM SoC.


Applied on mvebu/arm64

Thanks,

Gregory

>
> Yours,
> Linus Walleij

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2017-06-21 12:53 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-12 15:34 [PATCH v3 0/9] Add support for the pin and gpio controllers on the Marvell Armada 7K/8K Gregory CLEMENT
2017-06-12 15:34 ` [PATCH v3 1/9] gpio: mvebu: fix regmap_update_bits usage Gregory CLEMENT
2017-06-16  9:18   ` Linus Walleij
2017-06-12 15:34 ` [PATCH v3 2/9] pinctrl: mvebu: remove the offset property for regmap Gregory CLEMENT
2017-06-16  9:20   ` Linus Walleij
2017-06-12 15:34 ` [PATCH v3 3/9] pinctrl: avoid PLAT_ORION dependency Gregory CLEMENT
2017-06-16  9:21   ` Linus Walleij
2017-06-12 15:34 ` [PATCH v3 4/9] arm64: marvell: enable the Armada 7K/8K pinctrl driver Gregory CLEMENT
2017-06-16  9:22   ` Linus Walleij
2017-06-21 12:53     ` Gregory CLEMENT
2017-06-12 15:34 ` [PATCH v3 5/9] pinctrl: mvebu: add driver for Armada AP806 pinctrl Gregory CLEMENT
2017-06-16  9:23   ` Linus Walleij
2017-06-12 15:34 ` [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl Gregory CLEMENT
2017-06-16  9:24   ` Linus Walleij
2017-06-16  9:26   ` Linus Walleij
2017-06-12 15:34 ` [PATCH v3 7/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K Gregory CLEMENT
2017-06-20 14:34   ` Gregory CLEMENT
2017-06-12 15:34 ` [PATCH v3 8/9] gpio: mvebu: Add support for the Armada 7K/8K SoCs Gregory CLEMENT
2017-06-16  9:29   ` Linus Walleij
2017-06-12 15:35 ` [PATCH v3 9/9] arm64: dts: marvell: add gpio support for Armada 7K/8K Gregory CLEMENT
2017-06-20 14:34   ` Gregory CLEMENT

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