From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3881AC4361B for ; Fri, 11 Dec 2020 23:43:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F296923359 for ; Fri, 11 Dec 2020 23:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437056AbgLKXHJ (ORCPT ); Fri, 11 Dec 2020 18:07:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436997AbgLKXGj (ORCPT ); Fri, 11 Dec 2020 18:06:39 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6349FC0613CF for ; Fri, 11 Dec 2020 15:05:59 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id 23so15533014lfg.10 for ; Fri, 11 Dec 2020 15:05:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VPtMdGDRGuPEDGFmGnMvWlPbwtTye9nLOQ6zo2Mm3+s=; b=Tkxo8ubznZ/ihmwdGKwM0mnEC/9Inp+35eFt9HZ4SSZ8hVM2LajmncJVbJ8vVT9g7Y Bzevfd9OPqrtR7vCmS+Qyq9Q66deWC7tSue0PfNWMwfZw+4NMc6PVS3sMyL2AEgdJLVQ bs5Q8FBifb8fdc0t8MaeXkMsujAtyFcoVR93gBdo3ts2xXxu84uSsSc7nvDA31bMjA0T zyDFK0CL+q56OwKRrpoRUSRwndyj0xZxR5Awy2lgC48HQMSVM7YiZzG6POcphjwjahwN rIia2uSFw7gU6bSo0F+0LAg6gQCxPIftjemfQbohCg3tLqSw2jxFdpQ51oypEL8ksD+W HPYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VPtMdGDRGuPEDGFmGnMvWlPbwtTye9nLOQ6zo2Mm3+s=; b=B3wqZkra21c+84+zQizkpPwqHD9vllSl2IfGgSsOjZ8/q20gycFn5/5ZSYQWGV3/GS BID2lI7NLyPST9fwl22b4gxnm2Dh9mxE5SkQ3Y9Oxw5cAlPj8qxCqI6YIggKrPBhWxSr nOZjIgZQmHTjqOkznGTzFZJIErdVqqScvQ+GyutXQfBuO3ynW7RcGHZHrDtiCI9d2TZD mwhZXIc+dwPpKvvLxKdz311191aijkCYVRqbyfut8V88iO+reUCDdURATpGn0gH07ku6 jhy2jcpjZyT384anwu2rK0q9UfMNoDE6B9pN7f98Vj2SDXzg26Q08jcEFzHPltqHjvEF ZbYA== X-Gm-Message-State: AOAM533pwoX3oajdow3IxdWWeR+EODI0hLm1xMvv3mdkuK5JjtLUcesZ /kixT+1mdhcDYkTNekkaoFnVTdxnK3qRQpZe2nD+WzZGQgjDml9Q X-Google-Smtp-Source: ABdhPJyG4JiWO5sICrhd+prNYw2YnrYATbC3tLV3EewLAZiuaES/S08tUz/dKCFSdAJ+lv7Ji7zysfJtwScFy5P1idI= X-Received: by 2002:a19:7d84:: with SMTP id y126mr5515292lfc.586.1607727957931; Fri, 11 Dec 2020 15:05:57 -0800 (PST) MIME-Version: 1.0 References: <20201211094138.2863677-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20201211094138.2863677-2-nobuhiro1.iwamatsu@toshiba.co.jp> In-Reply-To: <20201211094138.2863677-2-nobuhiro1.iwamatsu@toshiba.co.jp> From: Linus Walleij Date: Sat, 12 Dec 2020 00:05:47 +0100 Message-ID: Subject: Re: [PATCH v4 1/4] dt-bindings: gpio: Add bindings for Toshiba Visconti GPIO Controller To: Nobuhiro Iwamatsu , Marc Zyngier Cc: Rob Herring , Punit Agrawal , yuji2.ishikawa@toshiba.co.jp, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux ARM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Rob Herring Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Looping in Marc here: On Fri, Dec 11, 2020 at 1:43 AM Nobuhiro Iwamatsu wrote: > Add bindings for the Toshiba Visconti GPIO Controller. > > Signed-off-by: Nobuhiro Iwamatsu > Reviewed-by: Rob Herring > Reviewed-by: Punit Agrawal (...) > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; This is an hierarchical IRQ controller. (These IRQs are mapped 1-to-1 to IRQ lines.) I was under the impression that we don't encode interrupts into the GPIO controller like this when we have that. Instead, hardcode these into the driver. The compatible string gives away how the local offsets map to the GIC IRQs. Add no interrupts to the node but make sure that the GIC is the parent. (Should be default.) Compare e.g. Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt Which has a similar "some hierarchical IRQs" setup. Yours, Linus Walleij