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From: Linus Walleij <linus.walleij@linaro.org>
To: "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@intel.com>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	"Raja Subramanian,
	Lakshmi Bai"  <lakshmi.bai.raja.subramanian@intel.com>,
	"Saha, Tamal" <tamal.saha@intel.com>
Subject: Re: [PATCH v3 2/2] pinctrl: Add Intel Keem Bay pinctrl driver
Date: Fri, 30 Jul 2021 11:13:34 +0200	[thread overview]
Message-ID: <CACRpkdbv77hjJ91h3fuLSYbpT+Yxd4X8_S7F+NsUw+QsKXN3Ww@mail.gmail.com> (raw)
In-Reply-To: <20210716162724.26047-3-lakshmi.sowjanya.d@intel.com>

Hi Lakshmi,

On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote:

> +       /*
> +        * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
> +        * and input values were checked to identify the source of the
> +        * Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
> +        */
> +       for_each_set_clump8(bit, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
> +               pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
> +               val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
> +               kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
> +
> +               /* Checks if the interrupt is enabled */
> +               if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
> +                       generic_handle_irq(kmb_irq);
> +       }

Aha there it is. "Half-hierarchical" with one IRQ handling 4 lines.

OK we can't do any better than this so this and the bindings
look fine.

I need to know how Andy think about merging, and then there is
an uninitialized ret in the mail from Dan Carpenter look into that
too.

In any case with minor nits fixed:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

  parent reply	other threads:[~2021-07-30  9:13 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-16 16:27 [PATCH v3 0/2] Add pinctrl support for Intel Keem Bay SoC lakshmi.sowjanya.d
2021-07-16 16:27 ` [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver lakshmi.sowjanya.d
2021-07-30  9:05   ` Linus Walleij
2021-07-30 11:29     ` Andy Shevchenko
2021-07-30 11:58       ` Linus Walleij
2021-07-30  9:15   ` Linus Walleij
2021-07-30 11:06     ` D, Lakshmi Sowjanya
2021-07-16 16:27 ` [PATCH v3 2/2] pinctrl: Add Intel Keem Bay " lakshmi.sowjanya.d
2021-07-28 19:16   ` [kbuild] " Dan Carpenter
2021-07-30 11:05     ` D, Lakshmi Sowjanya
2021-07-30  9:13   ` Linus Walleij [this message]
2021-07-30  9:32     ` Andy Shevchenko
2021-07-30 11:06       ` D, Lakshmi Sowjanya
2021-07-30 11:30         ` Andy Shevchenko

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