From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757182AbcG0Qug (ORCPT ); Wed, 27 Jul 2016 12:50:36 -0400 Received: from mail-io0-f196.google.com ([209.85.223.196]:34037 "EHLO mail-io0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756920AbcG0Quc (ORCPT ); Wed, 27 Jul 2016 12:50:32 -0400 MIME-Version: 1.0 In-Reply-To: <1468371785-53231-15-git-send-email-fenghua.yu@intel.com> References: <1468371785-53231-1-git-send-email-fenghua.yu@intel.com> <1468371785-53231-15-git-send-email-fenghua.yu@intel.com> From: Nilay Vaish Date: Wed, 27 Jul 2016 11:49:51 -0500 Message-ID: Subject: Re: [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code To: Fenghua Yu Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Tony Luck , Tejun Heo , Borislav Petkov , Stephane Eranian , Peter Zijlstra , Marcelo Tosatti , David Carrillo-Cisneros , Ravi V Shankar , Vikas Shivappa , Sai Prakhya , linux-kernel , x86 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12 July 2016 at 20:02, Fenghua Yu wrote: > From: Fenghua Yu > > Define two new cpuid leaves for CAT and CDP. The leaves are used in > x86_capability to avoid hard coded index. > > Clean comments for RDT, CAT_L3, and CDP_L3 cpufeatures. > > Signed-off-by: Fenghua Yu > Reviewed-by: Tony Luck > --- > arch/x86/include/asm/cpufeature.h | 2 ++ > arch/x86/include/asm/cpufeatures.h | 6 +++--- > arch/x86/include/asm/processor.h | 6 +++--- > arch/x86/kernel/cpu/common.c | 11 +++++++---- > 4 files changed, 15 insertions(+), 10 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index 483fb54..cd3b0bd 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -28,6 +28,8 @@ enum cpuid_leafs > CPUID_8000_000A_EDX, > CPUID_7_ECX, > CPUID_8000_0007_EBX, > + CPUID_10_0_EBX, > + CPUID_10_1_ECX, > }; > > #ifdef CONFIG_X86_FEATURE_NAMES > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 16489b3..588932a 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -220,7 +220,7 @@ > #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ > #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ > #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ > -#define X86_FEATURE_RDT ( 9*32+15) /* Resource Allocation */ > +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Director Technology */ > #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ > #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ > #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ > @@ -289,10 +289,10 @@ > #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ > > /* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 18 */ > -#define X86_FEATURE_CAT_L3 (18*32+ 1) /* Cache Allocation L3 */ > +#define X86_FEATURE_CAT_L3 (18*32+ 1) /* Cache Allocation L3 */ > > /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x00000010:1 (ecx), word 19 */ > -#define X86_FEATURE_CDP_L3 (19*32+ 2) /* Code data prioritization L3 */ > +#define X86_FEATURE_CDP_L3 (19*32+ 2) /* Code Data Prioritization L3 */ > > /* > * BUG word(s) > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h > index 598c9bc..308aa03 100644 > --- a/arch/x86/include/asm/processor.h > +++ b/arch/x86/include/asm/processor.h > @@ -119,9 +119,9 @@ struct cpuinfo_x86 { > int x86_cache_occ_scale; /* scale to bytes */ > int x86_power; > unsigned long loops_per_jiffy; > - /* Cache Allocation values: */ > - u16 x86_cache_max_cbm_len; > - u16 x86_cache_max_closid; > + /* Cache Allocation l3 values: */ > + u16 x86_l3_max_cbm_len; > + u16 x86_l3_max_closid; > /* cpuid returned max cores value: */ > u16 x86_max_cores; > u16 apicid; > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index a695e58..e945e70 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -716,14 +716,17 @@ void get_cpu_cap(struct cpuinfo_x86 *c) > u32 eax, ebx, ecx, edx; > > cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx); > - c->x86_capability[17] = ebx; > + c->x86_capability[CPUID_10_0_EBX] = ebx; > > if (cpu_has(c, X86_FEATURE_CAT_L3)) { > > cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx); > - c->x86_cache_max_closid = edx + 1; > - c->x86_cache_max_cbm_len = eax + 1; > - c->x86_capability[18] = ecx; > + c->x86_l3_max_closid = edx + 1; > + c->x86_l3_max_cbm_len = eax + 1; > + c->x86_capability[CPUID_10_1_ECX] = ecx; > + } else { > + c->x86_l3_max_closid = -1; > + c->x86_l3_max_cbm_len = -1; > } > } > I think this patch should be earlier in this patch series where the constants 17 and 18 were first used. Similarly the renaming of variables, I think, should be merged with the patch that originally introduced them. -- Nilay