From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758062AbcJHRNG (ORCPT ); Sat, 8 Oct 2016 13:13:06 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:35295 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752845AbcJHRMr (ORCPT ); Sat, 8 Oct 2016 13:12:47 -0400 MIME-Version: 1.0 In-Reply-To: <1475894763-64683-5-git-send-email-fenghua.yu@intel.com> References: <1475894763-64683-1-git-send-email-fenghua.yu@intel.com> <1475894763-64683-5-git-send-email-fenghua.yu@intel.com> From: Nilay Vaish Date: Sat, 8 Oct 2016 12:11:22 -0500 Message-ID: Subject: Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery To: Fenghua Yu Cc: Thomas Gleixner , "H. Peter Anvin" , Ingo Molnar , Tony Luck , Peter Zijlstra , Stephane Eranian , Borislav Petkov , Dave Hansen , Shaohua Li , David Carrillo-Cisneros , Ravi V Shankar , Sai Prakhya , Vikas Shivappa , linux-kernel , x86 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7 October 2016 at 21:45, Fenghua Yu wrote: > From: Fenghua Yu > > Check CPUID leaves for all the Resource Director Technology (RDT) > Cache Allocation Technology (CAT) bits. > > Prescence of allocation features: Presence > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 92a8308..64dd8274 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -196,6 +196,10 @@ > > #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ > > +#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */ > +#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 */ > +#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 */ > + > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ > @@ -220,6 +224,7 @@ > #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ > #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ > #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ > +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ > #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ > #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ > #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ I think these #defines are specific to Intel. I would prefer if we have _INTEL_ somewhere in them. -- Nilay