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From: Nilay Vaish <nilayvaish@gmail.com>
Date: Sat, 8 Oct 2016 12:12:07 -0500
Message-ID: <CACbG30_cKCS7Tz2GSosybPycEgGP444U8ebU8_A_AVr84JDs7g@mail.gmail.com>
Subject: Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel
 resource allocation user interface
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
        "H. Peter Anvin" <h.peter.anvin@intel.com>,
        Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Stephane Eranian <eranian@google.com>, Borislav Petkov <bp@suse.de>,
        Dave Hansen <dave.hansen@intel.com>, Shaohua Li <shli@fb.com>,
        David Carrillo-Cisneros <davidcc@google.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        Sai Prakhya <sai.praneeth.prakhya@intel.com>,
        Vikas Shivappa <vikas.shivappa@linux.intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
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On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
>
> +L3 details (code and data prioritization disabled)
> +--------------------------------------------------
> +With CDP disabled the L3 schemata format is:
> +
> +       L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
> +
> +L3 details (CDP enabled via mount option to resctrl)
> +----------------------------------------------------
> +When CDP is enabled, you need to specify separate cache bit masks for
> +code and data access. The generic format is:
> +
> +       L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...

Can we drop L3 here and instead say:
L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...

and similarly for without CDP as well.

--
Nilay