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Date: Wed, 18 May 2016 21:26:04 +0100
Message-ID: <CACvgo50-wnRYiYueRTqUT=PsUWu4NRm6bwZO8izaAZuf6-kMWQ@mail.gmail.com>
Subject: Re: [RFC 2/3] drm/mediatek: add support for Mediatek SoC MT2701
From: Emil Velikov <emil.l.velikov@gmail.com>
To: YT Shen <yt.shen@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
        ML dri-devel <dri-devel@lists.freedesktop.org>,
        Mark Rutland <mark.rutland@arm.com>,
        devicetree <devicetree@vger.kernel.org>,
        Russell King <linux@arm.linux.org.uk>, srv_heupstream@mediatek.com,
        Pawel Moll <pawel.moll@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        "Linux-Kernel@Vger. Kernel. Org" <linux-kernel@vger.kernel.org>,
        Mao Huang <littlecvr@chromium.org>, Rob Herring <robh+dt@kernel.org>,
        linux-mediatek@lists.infradead.org, Kumar Gala <galak@codeaurora.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Sascha Hauer <kernel@pengutronix.de>,
        LAKML <linux-arm-kernel@lists.infradead.org>
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On 18 May 2016 at 09:33, YT Shen <yt.shen@mediatek.com> wrote:

>> > @@ -108,6 +108,10 @@ int mtk_drm_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
>> >         int ret;
>> >
>> >         args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
>> > +       /*
>> > +       * align to 8 bytes since Mali requires it.
>> > +       */
>> > +       args->pitch = ALIGN(args->pitch, 8);
>> Are you sure we need this, based on the line just above ?
> I think bpp stands for bits per pixel, so width * bpp / 8 simply transfer from bits to bytes, which
> cannot guarantee align to 8.
>
You're absolutely correct. Reading the comment made me loose my mind
and completely misinterpret the division macro.

> I will remove this align part from the patch, this constraint is not from display controller.
Thank you !

Regards
Emil