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[209.85.217.44]) by smtp.gmail.com with ESMTPSA id o186sm1882026vka.15.2020.09.14.10.42.11 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Sep 2020 10:42:11 -0700 (PDT) Received: by mail-vs1-f44.google.com with SMTP id j6so355856vsg.8 for ; Mon, 14 Sep 2020 10:42:11 -0700 (PDT) X-Received: by 2002:a05:6102:10c2:: with SMTP id t2mr7966339vsr.10.1600105330813; Mon, 14 Sep 2020 10:42:10 -0700 (PDT) MIME-Version: 1.0 References: <1599019441-29308-1-git-send-email-srivasam@codeaurora.org> In-Reply-To: <1599019441-29308-1-git-send-email-srivasam@codeaurora.org> From: Doug Anderson Date: Mon, 14 Sep 2020 10:41:58 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver To: Srinivasa Rao Mandadapu Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rohit kumar , Srinivas Kandagatla , Ajit Pandey , Cheng-Yi Chiang Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tue, Sep 1, 2020 at 9:04 PM Srinivasa Rao Mandadapu wrote: > > From: Ajit Pandey > > Add the I2S controller node to sc7180 dtsi. > Add pinmux for primary and secondary I2S. > > Signed-off-by: Ajit Pandey > Signed-off-by: Cheng-Yi Chiang > Signed-off-by: Srinivasa Rao Mandadapu > --- > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index d46b383..db60ca5 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -676,6 +676,36 @@ > }; > }; > > + lpass_cpu: lpass@62f00000 { > + compatible = "qcom,sc7180-lpass-cpu"; > + > + reg = <0 0x62f00000 0 0x29000>; > + reg-names = "lpass-lpaif"; > + > + iommus = <&apps_smmu 0x1020 0>; > + > + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; > + > + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; > + > + clock-names = "pcnoc-sway-clk", "audio-core", > + "mclk0", "pcnoc-mport-clk", > + "mi2s-bit-clk0", "mi2s-bit-clk1"; > + > + > + #sound-dai-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + interrupts = ; > + interrupt-names = "lpass-irq-lpaif"; > + }; > + > sdhc_1: sdhci@7c4000 { Your node is still sorted incorrectly. Nodes with unit addresses should be sorted numerically. The number 0x62f00000 is greater than the number 0x7c4000. Thus your node should not be placed above "sdhci@7c4000". It should be placed somewhere further down in the file. > compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x7c4000 0 0x1000>, > @@ -1721,6 +1751,45 @@ > }; > }; > > + sec_mi2s_active: sec-mi2s-active { > + pinmux { > + pins = "gpio49", "gpio50", "gpio51"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio49", "gpio50", "gpio51";; nit: double-semi-colon.