Re: [PATCH v4 1/7] clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk

From: Doug Anderson <dianders@chromium.org>
To: Manu Gautam <mgautam@codeaurora.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh@kernel.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	LKML <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Vivek Gautam <vivek.gautam@codeaurora.org>,
	Evan Green <evgreen@chromium.org>,
	linux-arm-msm@vger.kernel.org, Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	"open list:ARM/QUALCOMM SUPPORT" <linux-soc@vger.kernel.org>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 1/7] clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk
Date: Thu, 29 Mar 2018 13:55:55 -0700	[thread overview]
Message-ID: <CAD=FV=UXvf+_rvbFGrHAQ1N0kbrMR_c2=LBVD=AMuL6DAjWO+Q@mail.gmail.com> (raw)
In-Reply-To: <1522321466-21755-2-git-send-email-mgautam@codeaurora.org>

Hi,

On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgautam@codeaurora.org> wrote:
> The USB and PCIE pipe clocks are sourced from external clocks
> inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
> clocks is dependent on PHY initialization sequence hence
> update halt_check to BRANCH_HALT_DELAY for these clocks so
> that clock status bit is not polled when enabling or disabling
> the clocks. It allows to simplify PHY client driver code which
> is both user and source of the pipe_clk and avoid error logging
> related status check on clk_disable/enable.
>
> Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 4 ++++
>  1 file changed, 4 insertions(+)

As per my feedback on <https://patchwork.kernel.org/patch/10314937/>,
I'm not a fan of this.  Hopefully we can adjust the PHY driver so it's
not needed.

-Doug