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[209.85.222.42]) by smtp.gmail.com with ESMTPSA id c9-v6sm54921uak.19.2018.08.16.13.49.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Aug 2018 13:49:42 -0700 (PDT) Received: by mail-ua1-f42.google.com with SMTP id y10-v6so4501040uao.4 for ; Thu, 16 Aug 2018 13:49:42 -0700 (PDT) X-Received: by 2002:ab0:5ac5:: with SMTP id x5-v6mr20881024uae.97.1534452582325; Thu, 16 Aug 2018 13:49:42 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a1f:cd5:0:0:0:0:0 with HTTP; Thu, 16 Aug 2018 13:49:41 -0700 (PDT) In-Reply-To: <20180816200648.90458-2-swboyd@chromium.org> References: <20180816200648.90458-1-swboyd@chromium.org> <20180816200648.90458-2-swboyd@chromium.org> From: Doug Anderson Date: Thu, 16 Aug 2018 13:49:41 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 1/3] pinctrl: msm: Really mask level interrupts to prevent latching To: Stephen Boyd Cc: Linus Walleij , LKML , "open list:GPIO SUBSYSTEM" , linux-arm-msm , Bjorn Andersson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd wrote: > The interrupt controller hardware in this pin controller has two status > enable bits. The first "normal" status enable bit enables or disables > the summary interrupt line being raised when a gpio interrupt triggers > and the "raw" status enable bit allows or prevents the hardware from > latching an interrupt into the status register for a gpio interrupt. > Currently we just toggle the "normal" status enable bit in the mask and > unmask ops so that the summary irq interrupt going to the CPU's > interrupt controller doesn't trigger for the masked gpio interrupt. > > For a level triggered interrupt, the flow would be as follows: the pin > controller sees the interrupt, latches the status into the status > register, raises the summary irq to the CPU, summary irq handler runs > and calls handle_level_irq(), handle_level_irq() masks and acks the gpio > interrupt, the interrupt handler runs, and finally unmask the interrupt. > When the interrupt handler completes, we expect that the interrupt line > level will go back to the deasserted state so the genirq code can unmask > the interrupt without it triggering again. > > If we only mask the interrupt by clearing the "normal" status enable bit > then we'll ack the interrupt but it will continue to show up as pending > in the status register because the raw status bit is enabled, the > hardware hasn't deasserted the line, and thus the asserted state latches > into the status register again. When the hardware deasserts the > interrupt the pin controller still thinks there is a pending unserviced > level interrupt because it latched it earlier. This behavior causes > software to see an extra interrupt for level type interrupts each time > the interrupt is handled. > > Let's fix this by clearing the raw status enable bit for level type > interrupts so that the hardware stops latching the status of the > interrupt after we ack it. We don't do this for edge type interrupts > because it seems that toggling the raw status enable bit for edge type > interrupts causes spurious edge interrupts. > > Cc: Bjorn Andersson > Cc: Doug Anderson > Signed-off-by: Stephen Boyd > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) Reviewed-by: Douglas Anderson NOTE: IMO we should land this fix even if we continue to have debate on patch #2 and #3 since this fixes a definite problem. -Doug