From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751060AbeC0E0x (ORCPT ); Tue, 27 Mar 2018 00:26:53 -0400 Received: from mail-vk0-f42.google.com ([209.85.213.42]:33312 "EHLO mail-vk0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750881AbeC0E0v (ORCPT ); Tue, 27 Mar 2018 00:26:51 -0400 X-Google-Smtp-Source: AG47ELsEbIjwtCHY4nSt9U0KQ8+X6550U1O1vS2AUKekqlZpD3Mc+ErP8Xf5k/HURC/LJ93/cjlH3DoA92hPJr6ev/M= MIME-Version: 1.0 In-Reply-To: <1521785487-29866-2-git-send-email-mgautam@codeaurora.org> References: <1521785487-29866-1-git-send-email-mgautam@codeaurora.org> <1521785487-29866-2-git-send-email-mgautam@codeaurora.org> From: Doug Anderson Date: Mon, 26 Mar 2018 21:26:49 -0700 X-Google-Sender-Auth: GnUKBH3DQnGmcScjILUGGDOTHhY Message-ID: Subject: Re: [PATCH v3 1/6] phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS To: Manu Gautam Cc: Kishon Vijay Abraham I , LKML , devicetree@vger.kernel.org, Rob Herring , linux-arm-msm@vger.kernel.org, Vivek Gautam , Varadarajan Narayanan , Viresh Kumar , Wei Yongjun , Fengguang Wu Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Manu On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam wrote: > QMP PHY for USB mode requires pipe_clk for calibration and PLL lock > to take place. This clock is output from PHY to GCC clock_ctl and then > fed back to QMP PHY and is available from PHY only after PHY is reset > and initialized, hence it can't be enabled too early in initialization > sequence. > > Signed-off-by: Manu Gautam > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) So it's now new with this patch, but it's more obvious with this patch. It seems like "UFS/PCIE" is kinda broken w/ respect to how it controls its clock. Specifically: * If you init the PHY but don't power it on, then you "exit" the PHY: you'll disable/unprepare "pipe_clk" even though you never prepare/enabled it. * If you init the PHY, power it on, power it off, power it on, and exit the PHY: you'll leave the clock prepared one extra time. Specifically I'd expect: for UFS/PCIE the disable/unprepare should be symmetric with the enable/prepare and should be in "power off", not in exit. ...or did I miss something? Interestingly, your patch fixes this problem for USB3 (where init/exit are now symmetric), but leaves the problem there for UFS/PCIE. -Doug