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[209.85.166.174]) by smtp.gmail.com with ESMTPSA id r22sm3837471ilb.25.2019.12.06.04.25.32 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2019 04:25:32 -0800 (PST) Received: by mail-il1-f174.google.com with SMTP id t17so6040357ilm.13 for ; Fri, 06 Dec 2019 04:25:32 -0800 (PST) X-Received: by 2002:a92:46c8:: with SMTP id d69mr14733574ilk.168.1575635132283; Fri, 06 Dec 2019 04:25:32 -0800 (PST) MIME-Version: 1.0 References: <20191108092824.9773-1-rnayak@codeaurora.org> <20191108092824.9773-14-rnayak@codeaurora.org> In-Reply-To: <20191108092824.9773-14-rnayak@codeaurora.org> From: Doug Anderson Date: Fri, 6 Dec 2019 20:25:20 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 13/13] arm64: dts: sc7180: Add qupv3_0 and qupv3_1 To: Rajendra Nayak Cc: Andy Gross , Rob Herring , Bjorn Andersson , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Matthias Kaehlcke , Stephen Boyd , Roja Rani Yarubandi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Nov 8, 2019 at 5:29 PM Rajendra Nayak wrote: > > From: Roja Rani Yarubandi > > Add QUP SE instances configuration for sc7180. > > Signed-off-by: Roja Rani Yarubandi > Signed-off-by: Rajendra Nayak > Reviewed-by: Stephen Boyd > --- > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ > arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ > 2 files changed, 821 insertions(+) Comments below could be done in a follow-up patch if it makes more sense. > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index e1d6278d85f7..666e9b92c7ad 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi At the top of this file, please add aliases for all i2c and spi devices (like sdm845 did). Right now trying to use command line i2c tools is super confusing because busses are super jumbled. > + i2c2: i2c@888000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00888000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi2? > + i2c4: i2c@890000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00890000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi4? > + i2c7: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a84000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c7_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi7? > + i2c9: i2c@a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a8c000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c9_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi9? > + qup_spi1_default: qup-spi1-default { > + pinmux { > + pins = "gpio0", "gpio1", > + "gpio2", "gpio3", > + "gpio12", "gpio94"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. > + qup_spi6_default: qup-spi6-default { > + pinmux { > + pins = "gpio59", "gpio60", > + "gpio61", "gpio62", > + "gpio68", "gpio72"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. > + qup_spi10_default: qup-spi10-default { > + pinmux { > + pins = "gpio86", "gpio87", > + "gpio88", "gpio89", > + "gpio90", "gpio91"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. -Doug