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[209.85.221.178]) by smtp.gmail.com with ESMTPSA id d133sm4682015vke.19.2019.05.17.16.58.00 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 16:58:00 -0700 (PDT) Received: by mail-vk1-f178.google.com with SMTP id l199so2494502vke.3 for ; Fri, 17 May 2019 16:58:00 -0700 (PDT) X-Received: by 2002:a1f:d884:: with SMTP id p126mr1000822vkg.70.1558137479874; Fri, 17 May 2019 16:57:59 -0700 (PDT) MIME-Version: 1.0 References: <20190507234857.81414-1-dianders@chromium.org> In-Reply-To: <20190507234857.81414-1-dianders@chromium.org> From: Doug Anderson Date: Fri, 17 May 2019 16:57:47 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] phy: rockchip-dp: Avoid power leak by leaving the PHY power on To: Elaine Zhang , Caesar Cc: Lin Huang , "open list:ARM/Rockchip SoC..." , Derek Basehore , Matthias Kaehlcke , Ryan Case , Guenter Roeck , LKML , Linux ARM , Kishon Vijay Abraham I , Heiko Stuebner Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Elaine and Caesar, On Tue, May 7, 2019 at 4:50 PM Douglas Anderson wrote: > > While testing a newer kernel on rk3288-based Chromebooks I found that > the power draw in suspend was higher on newer kernels compared to the > downstream Chrome OS 3.14 kernel. Specifically the power of an > rk3288-veyron-jerry board that I tested (as measured by the smart > battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel. > > I tracked the regression down to the fact that the "DP PHY" driver > didn't exist in our downstream 3.14. We relied on the eDP driver to > turn on the clock and relied on the fact that the power for the PHY > was default turned on. > > Specifically the thing that caused the power regression was turning > the eDP PHY _off_. Presumably there is some sort of power leak in the > system and when we turn the PHY off something is leaching power from > something else and causing excessive power draw. > > Doing a search through device trees shows that this PHY is only ever > used on rk3288. Presumably this power leak is present on all > rk3288-SoCs running upstream Linux so let's just whack the driver to > make sure we never turn off power. We'll still leave the parts that > turn _on_ the power and grab the clock, though. > > NOTES: > A) If someone can identify what this power leak is and fix it in some > other way we can revert this patch. > B) If someone can show that their particular board doesn't have this > power leak (maybe they have rails hooked up differently?) we can > perhaps add a device tree property indicating that for some boards > it's OK to turn this rail off. I don't want to add this property > until I know of a board that needs it. > > Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY") > Signed-off-by: Douglas Anderson > --- > As far as I know Yakir (the original author) is no longer at Rockchip. > I've added a few other Rockchip people and hopefully one of them can > help direct even if they're not directly responsible. > > drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) Can you help direct this to the right person? ...or should we just land it and assume it's fine? -Doug