From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424241AbcFMXFV (ORCPT ); Mon, 13 Jun 2016 19:05:21 -0400 Received: from mail-vk0-f41.google.com ([209.85.213.41]:34017 "EHLO mail-vk0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1424178AbcFMXFQ (ORCPT ); Mon, 13 Jun 2016 19:05:16 -0400 MIME-Version: 1.0 In-Reply-To: <20160610131052.GA9351@rob-hp-laptop> References: <1465339484-969-1-git-send-email-dianders@chromium.org> <1465339484-969-7-git-send-email-dianders@chromium.org> <20160608201923.GA20683@rob-hp-laptop> <20160610131052.GA9351@rob-hp-laptop> From: Doug Anderson Date: Mon, 13 Jun 2016 16:05:14 -0700 X-Google-Sender-Auth: ELx4-BTdHDrf69Q_yvPeJGD9qLk Message-ID: Subject: Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock To: Rob Herring Cc: Ulf Hansson , Kishon Vijay Abraham I , Heiko Stuebner , Shawn Lin , Ziyuan Xu , Brian Norris , Adrian Hunter , "open list:ARM/Rockchip SoC..." , "linux-mmc@vger.kernel.org" , "devicetree@vger.kernel.org" , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rob, On Fri, Jun 10, 2016 at 6:10 AM, Rob Herring wrote: > On Wed, Jun 08, 2016 at 01:52:20PM -0700, Doug Anderson wrote: >> Rob, >> >> On Wed, Jun 8, 2016 at 1:19 PM, Rob Herring wrote: >> > On Tue, Jun 07, 2016 at 03:44:39PM -0700, Douglas Anderson wrote: >> >> Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work >> >> with arasan,sdhci-5.1) need to know the card clock in order to function >> >> properly. Let's expose this clock using a standard device tree >> >> mechanism so that the PHY can get access to and query the card clock. >> > >> > Need to know the clock freq or need the clock? The former doesn't need >> > to be in DT. >> >> The PHY needs to know the card clock frequency. This clock clock >> frequency is known nowhere else in the system except the SDHCI driver >> since the SDHCI component takes its input clock and applies some >> dividers to get the card clock. In silicon, the SDHCI component and >> the PHY are separate and there is a physical clock signal going from >> the SDHCI component to the PHY component, so modeling this as a clock >> in in the device tree seems sane, doesn't it? > > Yes, please just re-word it to make it clear there is a connection. With > that, > > Acked-by: Rob Herring OK, done. Thanks for your review! -Doug