From: Doug Anderson <email@example.com> To: Xing Zheng <firstname.lastname@example.org> Cc: "Heiko Stuebner" <email@example.com>, "Frank Wang" <firstname.lastname@example.org>, "Brian Norris" <email@example.com>, "William wu" <firstname.lastname@example.org>, "Rob Herring" <email@example.com>, "Mark Rutland" <firstname.lastname@example.org>, "Catalin Marinas" <email@example.com>, "Will Deacon" <firstname.lastname@example.org>, "Caesar Wang" <email@example.com>, "Jianqun Xu" <firstname.lastname@example.org>, "Elaine Zhang" <email@example.com>, "firstname.lastname@example.org" <email@example.com>, "firstname.lastname@example.org" <email@example.com>, "firstname.lastname@example.org" <email@example.com>, "Dmitry Torokhov" <firstname.lastname@example.org>, "Tao Huang" <email@example.com>, "open list:ARM/Rockchip SoC..." <firstname.lastname@example.org>, "daniel.meng" <email@example.com>, "Kever Yang" <firstname.lastname@example.org>, 郑兴 <email@example.com> Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399 Date: Fri, 16 Dec 2016 09:28:21 -0800 [thread overview] Message-ID: <CAD=FV=W1BW6FSZ6MSxR6RhvtZyGsdQbz9vU_QshaQ5A65ENMCg@mail.gmail.com> (raw) In-Reply-To: <5853903D.firstname.lastname@example.org> Hi, On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng <email@example.com> wrote: > Hi Heiko, Doug, > > On 2016年12月16日 02:18, Heiko Stuebner wrote: > > Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson: > > > I still need to digest all of the things that were added to this > thread overnight, but nothing I've seen so far indicates that you need > the post-gated clock. AKA I still think you need to redo your patch > to replace: > > clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > <&cru SCLK_USBPHY0_480M_SRC>; > > with: > > clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > <&u2phy0>; > > Can you please comment on that? > > Also, with the change, the ehci will keep the clock (and thus the phy) > always > on. Does the phy-autosuspend even save anything now? > > In any case, could we make the clock-names entry sound nicer than > usbphy0_480m > please? bindings/usb/atmel-usb.txt calls its UTMI clock simply "usb_clk", > but > something like "utmi" should also work. > While at it you could also fix up the other clock names to something like > "host" and "arbiter" or so?. > > > Heiko > > > The usbphy related clock tress like this: > > > Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only > enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK. > > And the naming style of the "hclk_host0" keep the name "hclk_host0" on the > clcok tree diagram: > > > Therefore, could we rename the clock name like this: > ---- > for usb_host0_ehci and usb_host0_ohci: > clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > <&cru SCLK_U2PHY0>; > clock-names = "hclk_host0", "hclk_host0_arb", > "sclk_u2phy0"; > > for usb_host1_ehci and usb_host1_ohci: > clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, > <&cru SCLK_U2PHY1>; > clock-names = "hclk_host1", "hclk_host1_arb", > "sclk_u2phy1"; > ---- > > BTW, the "arb" is an abbreviation for arbiter. You don't specify what this new "SCLK_U2PHY0" ID is, so it's a little hard for me to know what you're intending. ...however, I still don't see any reason why you can't just use the solution I proposed. Specifying the clock as "<&u2phy0>" is the correct thing to do. The input clock to the EHCI driver is exactly the clock provided by the USB PHY with no gate in between (just as I said). There is no reason to somehow buffer it by the cru. The cru doesn't see this clock and has no reason to be involved. > Thanks. Note that there were many other comments on this thread besides mine. Are you planning to address any of them? -Doug
next prev parent reply other threads:[~2016-12-16 17:28 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-12-14 10:11 [PATCH 0/3] Add and export clk-480m clocks for ehci and ohci on RK3399 Xing Zheng 2016-12-14 10:11 ` [PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs Xing Zheng 2016-12-15 0:27 ` Doug Anderson 2016-12-14 10:11 ` [PATCH 2/3] clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1 Xing Zheng 2016-12-15 0:28 ` Doug Anderson 2016-12-14 10:11 ` [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399 Xing Zheng 2016-12-15 0:10 ` Doug Anderson 2016-12-15 0:47 ` Brian Norris 2016-12-15 1:18 ` Brian Norris 2016-12-15 2:41 ` Xing Zheng 2016-12-15 3:20 ` Brian Norris 2016-12-15 6:41 ` Frank Wang 2016-12-15 16:34 ` Doug Anderson 2016-12-15 18:18 ` Heiko Stuebner [not found] ` <5853903D.firstname.lastname@example.org> 2016-12-16 17:28 ` Doug Anderson [this message] 2016-12-21 10:44 ` Xing Zheng 2016-12-17 1:20 ` Heiko Stuebner
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