[PATCH] arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor

[PATCH] arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor

[Douglas Anderson]

From: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>

On coachz it could be observed that SPI_CLK voltage level was only
1.4V during active transfers because the drive strength was too
weak. The line hadn't finished slewing up by the time we started
driving it down again. Using a drive strength of 8 lets us achieve the
correct voltage level of 1.8V.

Though the worst problems were observed on coachz hardware, let's do
this across the board for trogdor devices. Scoping other boards shows
that this makes the clk line look nicer on them too and doesn't
introduce any problems.

Only the clk line is adjusted, not any data lines. Because SPI isn't a
DDR protocol we only sample the data lines on either rising or falling
edges, not both. That means the clk line needs to toggle twice as fast
as data lines so having the higher drive strength is more important
there.

Signed-off-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
[dianders: Adjust author real name; adjust commit message]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---

 arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 24d293ef56d7..c11e07959a63 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -981,6 +981,7 @@ pinconf {
 &qspi_clk {
 	pinconf {
 		pins = "gpio63";
+		drive-strength = <8>;
 		bias-disable;
 	};
 };
-- 
2.31.1.607.g51e8a6a459-goog

Re: [PATCH] arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor

[Doug Anderson]

Bjorn,

On Mon, May 10, 2021 at 7:53 AM Douglas Anderson <dianders@chromium.org> wrote:
>
> From: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
>
> On coachz it could be observed that SPI_CLK voltage level was only
> 1.4V during active transfers because the drive strength was too
> weak. The line hadn't finished slewing up by the time we started
> driving it down again. Using a drive strength of 8 lets us achieve the
> correct voltage level of 1.8V.
>
> Though the worst problems were observed on coachz hardware, let's do
> this across the board for trogdor devices. Scoping other boards shows
> that this makes the clk line look nicer on them too and doesn't
> introduce any problems.
>
> Only the clk line is adjusted, not any data lines. Because SPI isn't a
> DDR protocol we only sample the data lines on either rising or falling
> edges, not both. That means the clk line needs to toggle twice as fast
> as data lines so having the higher drive strength is more important
> there.
>
> Signed-off-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
> [dianders: Adjust author real name; adjust commit message]
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>
>  arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 +
>  1 file changed, 1 insertion(+)

I think this patch is ready to land and it's what we're now using in
the Chrome OS tree. See <https://crrev.com/c/2821728>.

-Doug