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[209.85.166.176]) by smtp.gmail.com with ESMTPSA id w15sm3867573iol.86.2020.01.16.10.27.22 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jan 2020 10:27:22 -0800 (PST) Received: by mail-il1-f176.google.com with SMTP id v15so19123467iln.0 for ; Thu, 16 Jan 2020 10:27:22 -0800 (PST) X-Received: by 2002:a92:8d8e:: with SMTP id w14mr4672100ill.187.1579199241984; Thu, 16 Jan 2020 10:27:21 -0800 (PST) MIME-Version: 1.0 References: <20200116141912.15465-1-saiprakash.ranjan@codeaurora.org> <20200116153235.GA18909@willie-the-truck> <1a3f9557fa52ce2528630434e9a49d98@codeaurora.org> In-Reply-To: <1a3f9557fa52ce2528630434e9a49d98@codeaurora.org> From: Doug Anderson Date: Thu, 16 Jan 2020 10:27:08 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] arm64: Add KRYO{3,4}XX CPU cores to spectre-v2 safe list To: Sai Prakash Ranjan Cc: Will Deacon , Jeffrey Hugo , Catalin Marinas , Marc Zyngier , Andre Przywara , Mark Rutland , LKML , linux-arm-msm , Linux ARM , Stephen Boyd , Bjorn Andersson , Matthias Kaehlcke , James Morse Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Jan 16, 2020 at 8:11 AM Sai Prakash Ranjan wrote: > > Hi Will, > > On 2020-01-16 21:02, Will Deacon wrote: > > [+Jeffrey] > > > > On Thu, Jan 16, 2020 at 07:49:12PM +0530, Sai Prakash Ranjan wrote: > >> KRYO3XX silver CPU cores and KRYO4XX silver, gold CPU cores > >> are not affected by Spectre variant 2. Add them to spectre_v2 > >> safe list to correct ARM_SMCCC_ARCH_WORKAROUND_1 warning and > >> vulnerability sysfs value. > >> > >> Signed-off-by: Sai Prakash Ranjan > >> --- > >> arch/arm64/include/asm/cputype.h | 6 ++++++ > >> arch/arm64/kernel/cpu_errata.c | 3 +++ > >> 2 files changed, 9 insertions(+) > >> > >> diff --git a/arch/arm64/include/asm/cputype.h > >> b/arch/arm64/include/asm/cputype.h > >> index aca07c2f6e6e..7219cddeba66 100644 > >> --- a/arch/arm64/include/asm/cputype.h > >> +++ b/arch/arm64/include/asm/cputype.h > >> @@ -85,6 +85,9 @@ > >> #define QCOM_CPU_PART_FALKOR_V1 0x800 > >> #define QCOM_CPU_PART_FALKOR 0xC00 > >> #define QCOM_CPU_PART_KRYO 0x200 > >> +#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 > >> +#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 > >> +#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 > > > > Jeffrey is the only person I know who understands the CPU naming here, > > so > > I've added him in case this needs either renaming or extending to cover > > other CPUs. I wouldn't be at all surprised if we need a function call > > rather than a bunch of table entries... > > > > That said, the internet claims that KRYO4XX gold is based on > > Cortex-A76, > > and so CSV2 should be set... > > > > Yes the internet claims are true and CSV2 is set. SANITY check logs in > here show ID_PFR0_EL1 - https://lore.kernel.org/patchwork/patch/1138457/ I'm probably just being a noob here and am confused, but if CSV2 is set then why do you need your patch at all? The code I see says that if CSV2 is set then we don't even check the spectre_v2_safe_list(). -Doug