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[209.85.128.50]) by smtp.gmail.com with ESMTPSA id 9-20020a170906210900b0078d21574986sm1838560ejt.203.2022.10.12.14.42.38 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Oct 2022 14:42:39 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id c7-20020a05600c0ac700b003c6cad86f38so1983108wmr.2 for ; Wed, 12 Oct 2022 14:42:38 -0700 (PDT) X-Received: by 2002:a05:600c:5488:b0:3b5:634:731 with SMTP id iv8-20020a05600c548800b003b506340731mr3906447wmb.188.1665610958124; Wed, 12 Oct 2022 14:42:38 -0700 (PDT) MIME-Version: 1.0 References: <20221010114417.29859-1-krzysztof.kozlowski@linaro.org> <20221010114417.29859-2-krzysztof.kozlowski@linaro.org> In-Reply-To: <20221010114417.29859-2-krzysztof.kozlowski@linaro.org> From: Doug Anderson Date: Wed, 12 Oct 2022 14:42:25 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/6] arm64: dts: qcom: sdm845-db845c: correct SPI2 pins drive strength To: Krzysztof Kozlowski Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Rob Clark , Lee Jones , Arnd Bergmann , Sudeep Holla , Vinod Koul , Xilin Wu , Molly Sophia , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Mon, Oct 10, 2022 at 4:46 AM Krzysztof Kozlowski wrote: > > The pin configuration (done with generic pin controller helpers and > as expressed by bindings) requires children nodes with either: > 1. "pins" property and the actual configuration, > 2. another set of nodes with above point. > > The qup_spi2_default pin configuration uses alreaady the second method > with a "pinmux" child, so configure drive-strength similarly in > "pinconf". Otherwise the PIN drive strength would not be applied. > > Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") > Cc: > Signed-off-by: Krzysztof Kozlowski > > --- > > Not tested on hardware. > > Changes since v1: > 1. Put it under pinconf instead of pinmux, as suggested by Doug. I notice that there are other two patches in the series that put the configuration info under the mux node. ;-) They are with SoCs / boards that I wasn't really involved in and so I won't do anything to block them from landing but, as per my replies to v1 it's not my favorite... In any case, this patch here looks great to me. Thanks! Looking forward to seeing these converted over to the scheme that your sc7180 patches used. Reviewed-by: Douglas Anderson