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[209.85.222.45]) by smtp.gmail.com with ESMTPSA id 29-v6sm805171vkd.42.2018.09.21.10.40.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Sep 2018 10:40:26 -0700 (PDT) Received: by mail-ua1-f45.google.com with SMTP id q7-v6so6102012uam.12 for ; Fri, 21 Sep 2018 10:40:25 -0700 (PDT) X-Received: by 2002:ab0:1601:: with SMTP id k1-v6mr13782085uae.83.1537551625587; Fri, 21 Sep 2018 10:40:25 -0700 (PDT) MIME-Version: 1.0 References: <20180920224055.164856-1-ryandcase@chromium.org> <153755105782.119890.8484594239463905156@swboyd.mtv.corp.google.com> In-Reply-To: <153755105782.119890.8484594239463905156@swboyd.mtv.corp.google.com> From: Doug Anderson Date: Fri, 21 Sep 2018 10:40:14 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation To: Stephen Boyd Cc: Mark Brown , ryandcase@chromium.org, boris.brezillon@bootlin.com, linux-arm-msm , Girish Mahadevan , devicetree@vger.kernel.org, LKML , linux-spi , Rob Herring , Mark Rutland Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Sep 21, 2018 at 10:31 AM Stephen Boyd wrote: > > Quoting Ryan Case (2018-09-20 15:40:54) > > diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt > > new file mode 100644 > > index 000000000000..ecfb1e2bd520 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt > > @@ -0,0 +1,36 @@ > > +Qualcomm Quad Serial Peripheral Interface (QSPI) > > + > > +The QSPI controller allows SPI protocol communication in single, dual, or quad > > +wire transmission modes for read/write access to slaves such as NOR flash. > > + > > +Required properties: > > +- compatible: Should contain: > > + "qcom,sdm845-qspi" > > Does someone have a more generic compatible string that can be added > here to indicate the type of quad SPI controller this is? I really doubt > this is a one-off hardware block for the specific SDM845 SoC. The compatible string used to be "qcom,qspi-v1". ...but Rob Herring requested [1] "an SoC specific compatible string". While we could do a compatible string like: "qcom,sdm845-qspi", "qcom,qspi-v1". I'm curious if that buys us anything. From all my previous experience with device tree it is fine to name a compatible string for a component based on the first SoC that used it. If we later find that this is also used in an "msm1234" we could always later do the compatible string for that device as: "qcom, msm1234-qspi", "qcom,sdm845-qspi" ...and we don't need to try to come up with a generic name. Obviously, though, I'll cede to whatever Rob says here though. -Doug [1] http://lkml.kernel.org/r/20180716222721.GA12854@rob-hp-laptop > > > +- reg: Should contain the base register location and length. > > +- interrupts: Interrupt number used by the controller. > > +- clocks: Should contain the core and AHB clock. > > +- clock-names: Should be "core" for core clock and "iface" for AHB clock. > > +