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[209.85.217.50]) by smtp.gmail.com with ESMTPSA id y74sm533385vkd.39.2020.12.11.14.15.00 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Dec 2020 14:15:00 -0800 (PST) Received: by mail-vs1-f50.google.com with SMTP id x26so5654587vsq.1 for ; Fri, 11 Dec 2020 14:15:00 -0800 (PST) X-Received: by 2002:a67:bd01:: with SMTP id y1mr8708522vsq.49.1607724899973; Fri, 11 Dec 2020 14:14:59 -0800 (PST) MIME-Version: 1.0 References: <20201209163818.v3.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid> <20201209163818.v3.3.I771b6594b2a4d5b7fe7e12a991a6640f46386e8d@changeid> <160763738065.1580929.11062492180508041591@swboyd.mtv.corp.google.com> In-Reply-To: <160763738065.1580929.11062492180508041591@swboyd.mtv.corp.google.com> From: Doug Anderson Date: Fri, 11 Dec 2020 14:14:48 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 3/3] pinctrl: qcom: Clear possible pending irq when remuxing GPIOs To: Stephen Boyd Cc: Jason Cooper , Linus Walleij , Marc Zyngier , Thomas Gleixner , linux-arm-msm , Bjorn Andersson , Srinivas Ramana , Maulik Shah , Neeraj Upadhyay , Rajendra Nayak , "open list:GPIO SUBSYSTEM" , Andy Gross , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Dec 10, 2020 at 1:56 PM Stephen Boyd wrote: > > Quoting Douglas Anderson (2020-12-09 16:41:03) > > Conceptually, we can envision the input on Qualcomm SoCs to pass > > through a bunch of blocks between coming into the chip and becoming a > > GPIO interrupt. From guessing and running a handful of tests, I > > believe that we can represent the state of the world with a drawing > > that looks something like this: > > > > +-----------------+ +-----------------+ +-----------------+ > > | INPUT | --> | PINMUX | | IS_INPUT | > > +-----------------+ | | --> | | > > | output bogus (?)| | output bogus (?)| > > | if not muxed | | if input disab. | > > +-----------------+ +-----------------+ > > | > > +---------------------------------------------------+--> to PDC > > | > > V > > +-----------------+ +-----------------+ +-----------------+ > > | INTR RAW ENABLE | | DETECTION LOGIC | | STATUS REGISTER | > > | | | | | | > > | output bogus (?)| --> | maybe handles | | latches inputs | > > | if disabled | | polarity diffs | --> | that are high | > > +-----------------+ | | | | > > | maybe debounces | | write 1 to clr | > > | level irqs | +-----------------+ > > +-----------------+ | > > | > > +---------------------------------------------------+ > > | > > V > > +-----------------+ > > | ENABLE | > > | | +-----------------+ > > | nothing passes | --> | SUMMARY IRQ | > > | through if | +-----------------+ > > | disabled | > > +-----------------+ > > This diagram doesn't make sense to me. I've gutted most of this code for v4 after Maulik pointed out why my testing was flawed. Hopefully v4 looks saner... -Doug