From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE75DC43331 for ; Mon, 11 Nov 2019 23:40:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74DD7214DB for ; Mon, 11 Nov 2019 23:40:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727438AbfKKXkF (ORCPT ); Mon, 11 Nov 2019 18:40:05 -0500 Received: from mail-oi1-f196.google.com ([209.85.167.196]:35785 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726923AbfKKXkE (ORCPT ); Mon, 11 Nov 2019 18:40:04 -0500 Received: by mail-oi1-f196.google.com with SMTP id n16so13138168oig.2 for ; Mon, 11 Nov 2019 15:40:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rYJ3hr5T5tZC4vSB8BbaPI2/bk6dIa1jNkM2nXBTPBI=; b=nFtBj/M8KtA8lR3cHWblAuQgt+FtDp+9rUVSz7E+UUMqNn5QKowIMB0xjZ8LXm1B/g eR4OsqMv27ZVmWI40oHtgntixm7dxXzqMRddS4ZwHVVQmszgtYO1uRU1ChYtRfKLjU1z 2knHOuQadur2EdCzEYoR1SMej1/nkTqXRdJYV29dd9MlDtXfmq3mUeeLUKZUs4RRyJ1+ gmzmd6MJHUAJBiBf50ogVZ4LHoS/nJVFLU3WXIESc1lAvCJi0KVSTaclGYkeiSkGwxKj A+WktAwbzoQN+5ZVPMDm7itA6GGE2SSC8i08t0tl0i06lKGyFgD6DznuxZRPV/DYZf2D OWIg== X-Gm-Message-State: APjAAAXjy95CUfE+hbRD3+bPFyBMz7kGZ3So8uwVcurUTscFTdjgnOnr Pymf5E6F1Wq+LZfH2V2tlpL4E+th X-Google-Smtp-Source: APXvYqxqEqNGm6TqPYNZNA2tXJ2n5Xd/iAqOlXrb51AN8akSpX1jBfackQQsV3W9dmeZ6b11Kd5uFQ== X-Received: by 2002:aca:417:: with SMTP id 23mr1376067oie.125.1573515603170; Mon, 11 Nov 2019 15:40:03 -0800 (PST) Received: from mail-oi1-f177.google.com (mail-oi1-f177.google.com. [209.85.167.177]) by smtp.gmail.com with ESMTPSA id h79sm5332530oib.3.2019.11.11.15.40.01 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 15:40:01 -0800 (PST) Received: by mail-oi1-f177.google.com with SMTP id v138so13104474oif.6 for ; Mon, 11 Nov 2019 15:40:01 -0800 (PST) X-Received: by 2002:aca:1205:: with SMTP id 5mr1320355ois.51.1573515600853; Mon, 11 Nov 2019 15:40:00 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> In-Reply-To: <20191108130123.6839-1-linux@rasmusvillemoes.dk> From: Li Yang Date: Mon, 11 Nov 2019 17:39:49 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 00/47] QUICC Engine support on ARM and ARM64 To: Rasmus Villemoes , David Miller , Scott Wood , Greg Kroah-Hartman , Timur Tabi , Qiang Zhao Cc: Christophe Leroy , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , lkml Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes wrote: > I'm generally ok with these enhencements and cleanups. But as the whole patch series touched multiple subsystems, I would like to collect the Acked-by from Scott, Greg and David if we want the whole series to go through the fsl/soc tree. Also Qiang, can you help to test the latest version and provide you Tested-by? Thanks. > There have been several attempts in the past few years to allow > building the QUICC engine drivers for platforms other than PPC. This > is yet another attempt. > > v3 can be found here: https://lore.kernel.org/lkml/20191101124210.14510-1-linux@rasmusvillemoes.dk/ > > v4 adds a some patches to fix (ab)use of IS_ERR_VALUE which fails when > sizeof(u32) != sizeof(long), i.e. on 64-bit platforms. Freescale > drivers are some of the last holdouts using that macro (outside of > arch/ and core mm code), so I decided trying to simply get rid of it > instead of papering over it by using a temporary long to store the > result in. Doing that I stumbled on some other things that should be > fixed. These are the new patches 34-45. > > Patch 35 from v3 (which added a PPC32 dependency to FSL_UCC_HDLC) is > gone from this version, so that that driver can indeed now be built > for arm and arm64. > > 1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe). > > 6-8 handle miscellaneous other ppcisms. > > 9-21 deal with qe_ic: Simplifying the driver significantly by removing > unused code, and removing the platform-specific initialization from > arch/powerpc/. > > 22-25 deal with raw access to devicetree properties in native endianness. > > 26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm. > > 34-45 deal with IS_ERR_VALUE() and some other things found while > digging around that part of the code. > > 46 adds a PPC32 dependency to UCC_GETH - it has some of the same > issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody > has requested that I allow that driver to be built for arm{,64}, so > instead of growing this series even bigger, I kept that addition. It's > trivial to remove if somebody cares enough to fix the build > errors/warnings and actually has a platform to test the result on. > > Finally patch 47 lifts the PPC32 restriction from QUICC_ENGINE. At the > request of Li Yang, it doesn't remove the PPC32 dependency but instead > changes it to PPC32 || ARM || ARM64 (or COMPILE_TEST), i.e. listing > the platforms that may have a QE. > > The series has been built and booted on both an mpc8309-based platform > (ppc) as well as an ls1021a-based platform (arm). The core QE code is > exercised on both, while I could only test the ucc_uart on arm, since > the uarts are not wired up on our mpc8309 board. Qiang Zhao reports > that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64) > board, I hope he'll formally add a Tested-by: to the relevant patches > since I don't have any arm64 board with QE. > > Rasmus Villemoes (47): > soc: fsl: qe: remove space-before-tab > soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs > soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers > soc: fsl: qe: introduce qe_io{read,write}* wrappers > soc: fsl: qe: avoid ppc-specific io accessors > soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic > soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 > soc: fsl: qe: drop unneeded #includes > soc: fsl: qe: drop assign-only high_active in qe_ic_init > soc: fsl: qe: remove pointless sysfs registration in qe_ic.c > soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx > soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ > powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ > powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Scott, What do you think about the PPC changes? > soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c > soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low > soc: fsl: qe: remove unused qe_ic_set_* functions > soc: fsl: qe: don't use NO_IRQ in qe_ic.c > soc: fsl: qe: make qe_ic_get_{low,high}_irq static > soc: fsl: qe: simplify qe_ic_init() > soc: fsl: qe: merge qe_ic.h headers into qe_ic.c > soc: fsl: qe: qe.c: use of_property_read_* helpers > soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() > soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu > soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() > soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl > soc/fsl/qe/qe.h: update include path for cpm.h > serial: ucc_uart: explicitly include soc/fsl/cpm.h > serial: ucc_uart: replace ppc-specific IO accessors > serial: ucc_uart: factor out soft_uart initialization > serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 > serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() > serial: ucc_uart: access __be32 field using be32_to_cpu Greg and Timur, What do you think about these serial changes. > soc: fsl: qe: change return type of cpm_muram_alloc() to s32 > soc: fsl: qe: make cpm_muram_free() return void > soc: fsl: qe: make cpm_muram_free() ignore a negative offset > soc: fsl: qe: drop broken lazy call of cpm_muram_init() > soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error > path > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c > soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() > soc: fsl: qe: drop pointless check in qe_sdma_init() > soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c > net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() > net/wan/fsl_ucc_hdlc: fix reading of __be16 registers > net/wan/fsl_ucc_hdlc: reject muram offsets above 64K > net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 David and Qiang, What do you think of the net changes? > soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE > > arch/powerpc/include/asm/cpm.h | 172 +------- > arch/powerpc/platforms/83xx/km83xx.c | 3 +- > arch/powerpc/platforms/83xx/misc.c | 23 -- > arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +- > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +- > arch/powerpc/platforms/83xx/mpc83xx.h | 7 - > arch/powerpc/platforms/85xx/common.c | 23 -- > arch/powerpc/platforms/85xx/corenet_generic.c | 12 - > arch/powerpc/platforms/85xx/mpc85xx.h | 2 - > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 -- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 - > arch/powerpc/platforms/85xx/twr_p102x.c | 16 - > drivers/net/ethernet/freescale/Kconfig | 2 +- > drivers/net/wan/fsl_ucc_hdlc.c | 23 +- > drivers/net/wan/fsl_ucc_hdlc.h | 2 +- > drivers/soc/fsl/qe/Kconfig | 3 +- > drivers/soc/fsl/qe/gpio.c | 34 +- > drivers/soc/fsl/qe/qe.c | 104 ++--- > drivers/soc/fsl/qe/qe_common.c | 50 +-- > drivers/soc/fsl/qe/qe_ic.c | 285 ++++++------- > drivers/soc/fsl/qe/qe_ic.h | 99 ----- > drivers/soc/fsl/qe/qe_io.c | 70 ++-- > drivers/soc/fsl/qe/qe_tdm.c | 8 +- > drivers/soc/fsl/qe/ucc.c | 26 +- > drivers/soc/fsl/qe/ucc_fast.c | 86 ++-- > drivers/soc/fsl/qe/ucc_slow.c | 60 ++- > drivers/soc/fsl/qe/usb.c | 2 +- > drivers/tty/serial/ucc_uart.c | 383 +++++++++--------- > include/soc/fsl/cpm.h | 171 ++++++++ > include/soc/fsl/qe/qe.h | 59 ++- > include/soc/fsl/qe/qe_ic.h | 135 ------ > include/soc/fsl/qe/ucc_fast.h | 4 +- > include/soc/fsl/qe/ucc_slow.h | 6 +- > 35 files changed, 770 insertions(+), 1158 deletions(-) > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h > create mode 100644 include/soc/fsl/cpm.h > delete mode 100644 include/soc/fsl/qe/qe_ic.h > > -- > 2.23.0 >