From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F40C433F5 for ; Tue, 5 Oct 2021 01:10:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 888C3613AC for ; Tue, 5 Oct 2021 01:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230260AbhJEBMl (ORCPT ); Mon, 4 Oct 2021 21:12:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229612AbhJEBMk (ORCPT ); Mon, 4 Oct 2021 21:12:40 -0400 Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93EE4C061749 for ; Mon, 4 Oct 2021 18:10:50 -0700 (PDT) Received: by mail-ot1-x335.google.com with SMTP id h9-20020a9d2f09000000b005453f95356cso23908279otb.11 for ; Mon, 04 Oct 2021 18:10:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:in-reply-to:references:from:user-agent:date:message-id :subject:to:cc; bh=rLYw2KrQ4s9yKh8fwXPTnJIwo3OAJ8FO94iCHD8cOyc=; b=NfweNdNukEeDOmICkjI+OAOsiFlhGgBdGGuE3YS7PPqAtBU/vvUP2YYgGsozM8MhDr xAdETSKZTxk+artDcSFycUCG6VpiP/8uGGZxPRj6+T772L+8572TOw4ceNhukT9YQzjh l8qD3NkacSCpPIvzktW3BEsh7ksMXKB5Vk2qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:in-reply-to:references:from :user-agent:date:message-id:subject:to:cc; bh=rLYw2KrQ4s9yKh8fwXPTnJIwo3OAJ8FO94iCHD8cOyc=; b=0LO3dAMJJ6JlzhgHWZoNB3JpJs6rtqVVXq+3Nvs6J1QNW2jXrLqCz19WqmVb+ao4pq bLi/K42+Ft61NsrxUZ1Xb+m+2WpdvNZFkt1HTmZ49TdqUHuBYSyBG/QKJguirR3pvkBP 3wwqTVQhbU/S8mKX4gMcxplEO2TfeKc3DOdxwFMtGIN5jNLwjILKJCEnbSspLuqA+PaD fg/wSfvYH65+A7UATp8uvvhxRZjlaF/jZnWRZm7Mjf9GPh/+w2x9yTUd9JVQfpWlfunN y83W6HwFMEnDtTmytDR1dXg/f3Awqb3k+u5CuE+GWtap1iY+kFLgTF5B9nzJ8qRJ/CT3 WIgg== X-Gm-Message-State: AOAM530LoNT8KKfYZd0wwN7kfUcOS6VstizPJe5HmZ2u1keHMxegV2XV LfYjVsvj8w7AxYPM8v8mqPIVCEYB9xf0es2lJRhHcg== X-Google-Smtp-Source: ABdhPJw/be4HaaJNo0lUyEzqEwnsmy31pjLpTnss9vmmL1BpHUvaF9IauV887aW6sUmfDgdNjMNrPLMCP754T3ywXq0= X-Received: by 2002:a9d:6a0f:: with SMTP id g15mr12319566otn.126.1633396249933; Mon, 04 Oct 2021 18:10:49 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Mon, 4 Oct 2021 21:10:49 -0400 MIME-Version: 1.0 In-Reply-To: <1633376488-545-4-git-send-email-pmaliset@codeaurora.org> References: <1633376488-545-1-git-send-email-pmaliset@codeaurora.org> <1633376488-545-4-git-send-email-pmaliset@codeaurora.org> From: Stephen Boyd User-Agent: alot/0.9.1 Date: Mon, 4 Oct 2021 21:10:49 -0400 Message-ID: Subject: Re: [PATCH v10 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board To: Prasad Malisetty , agross@kernel.org, bhelgaas@google.com, bjorn.andersson@linaro.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, svarbanov@mm-sol.com Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vbadigan@codeaurora.org, sallenki@codeaurora.org, manivannan.sadhasivam@linaro.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Prasad Malisetty (2021-10-04 12:41:26) > Enable PCIe controller and PHY for sc7280 IDP board. > Add specific NVMe GPIO entries for SKU1 and SKU2 support. > > Signed-off-by: Prasad Malisetty > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++ > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++ > 3 files changed, 67 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > index 272d5ca..b416f3d 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > @@ -462,6 +491,28 @@ > }; > > &tlmm { > + nvme_pwren_pin: nvme-pwren-pin { pin is sort of redundant but OK. It would be simpler without the pin postfix. > + function = "gpio"; > + bias-pull-up; Why is there a bias pull up on this enable pin? I'd expect to see a bias-disable as this is an output pin and there's no need for a pull. > + }; > + > + pcie1_reset_n: pcie1-reset-n { > + pins = "gpio2"; > + function = "gpio"; > + > + drive-strength = <16>; Why such a strong drive strength? > + output-low; > + bias-disable; > + }; > + > + pcie1_wake_n: pcie1-wake-n { > + pins = "gpio3"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-pull-up; > + }; > + > qup_uart7_sleep_cts: qup-uart7-sleep-cts { > pins = "gpio28"; > function = "gpio";