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[209.85.167.52]) by smtp.gmail.com with ESMTPSA id b14sm597131lji.25.2019.02.19.15.37.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 15:37:51 -0800 (PST) Received: by mail-lf1-f52.google.com with SMTP id g12so6542261lfb.13 for ; Tue, 19 Feb 2019 15:37:51 -0800 (PST) X-Received: by 2002:a19:ec0c:: with SMTP id b12mr19485118lfa.27.1550619118494; Tue, 19 Feb 2019 15:31:58 -0800 (PST) MIME-Version: 1.0 References: <1550394300-17420-1-git-send-email-yong.wu@mediatek.com> <1550394300-17420-14-git-send-email-yong.wu@mediatek.com> In-Reply-To: <1550394300-17420-14-git-send-email-yong.wu@mediatek.com> From: Evan Green Date: Tue, 19 Feb 2019 15:31:22 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 13/22] iommu/mediatek: Add mt8183 IOMMU support To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Robin Murphy , Rob Herring , Tomasz Figa , Will Deacon , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, yingjoe.chen@mediatek.com, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, Matthias Kaehlcke Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote: > > The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use > the ARM Short-descriptor like mt8173, and most of the HW registers > are the same. > > Here list main differences between mt8183 and mt8173/mt2712: > 1) mt8183 has only one M4U HW like mt8173 while mt2712 has two. > 2) mt8183 don't have the "bclk" clock, it use the EMI clock instead. > 3) mt8183 can support the dram over 4GB, but it doesn't call this "4GB > mode". > 4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent > the bit[33:32] in the physical address of the pgtable base, But the > standard ttbr0[1] means the S bit which is enabled defaultly, Hence, > we add a mask. > 5) mt8183 HW has a GALS modules, SMI should enable "has_gals" support. > 6) mt8183 need reset_axi like mt8173. > 7) the larb-id in smi-common is remapped. M4U should add its larbid_remap. > > Signed-off-by: Yong Wu Reviewed-by: Evan Green