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[209.85.167.48]) by smtp.gmail.com with ESMTPSA id a15-v6sm378512ljf.92.2018.08.07.12.57.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Aug 2018 12:57:20 -0700 (PDT) Received: by mail-lf1-f48.google.com with SMTP id u202-v6so12506966lff.9 for ; Tue, 07 Aug 2018 12:57:20 -0700 (PDT) X-Received: by 2002:a19:d484:: with SMTP id l126-v6mr14455132lfg.28.1533671840372; Tue, 07 Aug 2018 12:57:20 -0700 (PDT) MIME-Version: 1.0 References: <20180731224421.29062-1-ilina@codeaurora.org> <20180731224421.29062-5-ilina@codeaurora.org> In-Reply-To: <20180731224421.29062-5-ilina@codeaurora.org> From: Evan Green Date: Tue, 7 Aug 2018 12:56:43 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 4/4] arm64: dts: qcom: add wake up interrupts for GPIOs To: Lina Iyer Cc: marc.zyngier@arm.com, Stephen Boyd , Linus Walleij , Bjorn Andersson , rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rajendra Nayak , devicetree@vger.kernel.org, swboyd@chromium.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote: > > GPIOs that are wakeup capable have interrupt lines that are routed to > the always-on interrupt controller (PDC) in parallel to the pinctrl. The > interrupts listed here are the wake up lines corresponding to GPIOs. > > Signed-off-by: Lina Iyer > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 69 ++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 8ccce42885c1..96ef18ced85b 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -720,6 +720,75 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + interrupts-extended = <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, In order to get any GPIO interrupts on my board, I needed to add the summary IRQ first in this list. My reading of platform_get_irq is that "interrupts-extended" is queried before "interrupts", so we accidentally wire the summary IRQ to PDC 30. Given this, you can probably remove the regular "interrupts" property. -Evan > + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 36 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 37 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 38 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 39 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 41 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 42 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 43 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 44 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 45 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 46 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 52 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 54 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 57 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 58 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 59 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 60 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 61 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 62 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 63 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 64 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 65 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 66 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 67 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 68 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 69 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 70 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 71 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 72 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 73 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 74 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 75 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 79 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 80 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 81 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 82 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 83 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 84 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 85 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 86 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 90 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 91 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 92 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 95 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 97 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 98 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 99 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 100 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 102 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 103 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 104 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 105 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 106 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 107 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 108 IRQ_TYPE_LEVEL_HIGH>; > > qup_i2c0_default: qup-i2c0-default { > pinmux { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >