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[209.85.167.49]) by smtp.gmail.com with ESMTPSA id 67-v6sm4714932ljc.26.2019.02.19.15.38.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 15:38:14 -0800 (PST) Received: by mail-lf1-f49.google.com with SMTP id u21so16192650lfu.1 for ; Tue, 19 Feb 2019 15:38:14 -0800 (PST) X-Received: by 2002:a19:ae0b:: with SMTP id f11mr13049011lfc.104.1550619018042; Tue, 19 Feb 2019 15:30:18 -0800 (PST) MIME-Version: 1.0 References: <1550394300-17420-1-git-send-email-yong.wu@mediatek.com> <1550394300-17420-7-git-send-email-yong.wu@mediatek.com> In-Reply-To: <1550394300-17420-7-git-send-email-yong.wu@mediatek.com> From: Evan Green Date: Tue, 19 Feb 2019 15:29:41 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 06/22] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Robin Murphy , Rob Herring , Tomasz Figa , Will Deacon , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, yingjoe.chen@mediatek.com, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, Matthias Kaehlcke Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 17, 2019 at 1:07 AM Yong Wu wrote: > > MediaTek extend the arm v7s descriptor to support the dram over 4GB. > > In the mt2712 and mt8173, it's called "4GB mode", the physical address > is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it > is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the > bit32 is always enabled. thus, in the M4U, we always enable the bit9 > for all PTEs which means to enable bit32 of physical address. > > but in mt8183, M4U support the dram from 0x4000_0000 to 0x3_ffff_ffff > which isn't remaped. We extend the PTEs: the bit9 represent bit32 of > PA and the bit4 represent bit33 of PA. Meanwhile the iova still is > 32bits. > > In order to unify code, in the "4GB mode", we add the bit32 for the > physical address manually in our driver. > > Correspondingly, Adding bit32 and bit33 for the PA in the iova_to_phys > has to been moved into v7s. > > Regarding whether the pagetable address could be over 4GB, the mt8183 > support it while the previous mt8173 don't. thus keep it as is. > > Signed-off-by: Yong Wu > Reviewed-by: Robin Murphy > --- > Comparing the previous version, I add MTK_4GB quirk always since mtk_iommu > has already controlled the PA itself. Helped from Evan. Thanks for all the explanation on this one. I think I understand it now, and it looks good to me. Reviewed-by: Evan Green