From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>
Subject: Re: [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device
Date: Mon, 14 Jun 2021 21:34:05 +0800 [thread overview]
Message-ID: <CAEUhbmUvjFg7a4xr9p_r0qynwa5DAOejtV77XMUJvwfTOOFu1A@mail.gmail.com> (raw)
In-Reply-To: <20210612160422.330705-8-anup.patel@wdc.com>
On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V ACLINT specification is a modular specification and the
> ACLINT MTIMER device is compatible with the M-mode timer functionality
> of the CLINT device. This patch extends the CLINT driver to support
> both CLINT device and ACLINT MTIMER device.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
> 1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
> index dfdcd94c1fd5..ca329c450810 100644
> --- a/drivers/clocksource/timer-clint.c
> +++ b/drivers/clocksource/timer-clint.c
> @@ -2,8 +2,15 @@
> /*
> * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> *
> - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
> - * CLINT MMIO timer device.
> + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
> + * MMIO device which is a composite device capable of injecting M-mode
> + * software interrupts and M-mode timer interrupts.
> + *
> + * The RISC-V ACLINT specification is modular in nature and defines
> + * separate devices for M-mode software interrupt (MSWI), M-mode timer
> + * (MTIMER) and S-mode software interrupt (SSWI).
> + *
> + * This is a common driver for CLINT device and ACLINT MTIMER device.
> */
>
> #define pr_fmt(fmt) "clint: " fmt
> @@ -21,14 +28,20 @@
> #include <linux/smp.h>
> #include <linux/timex.h>
>
> -#ifndef CONFIG_RISCV_M_MODE
> +#ifdef CONFIG_RISCV_M_MODE
> #include <asm/clint.h>
> +
> +u64 __iomem *clint_time_val;
> +EXPORT_SYMBOL(clint_time_val);
> #endif
>
> #define CLINT_IPI_OFF 0
> #define CLINT_TIMER_CMP_OFF 0x4000
> #define CLINT_TIMER_VAL_OFF 0xbff8
>
> +#define ACLINT_MTIMER_CMP_OFF 0x0000
> +#define ACLINT_MTIMER_VAL_OFF 0x7ff8
> +
> /* CLINT manages IPI and Timer for RISC-V M-mode */
> static u32 __iomem *clint_ipi_base;
> static u64 __iomem *clint_timer_cmp;
> @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
> static unsigned long clint_timer_freq;
> static unsigned int clint_timer_irq;
>
> -#ifdef CONFIG_RISCV_M_MODE
> -u64 __iomem *clint_time_val;
> -EXPORT_SYMBOL(clint_time_val);
> -#endif
> -
> static void clint_send_ipi(const struct cpumask *target)
> {
> unsigned int cpu;
> @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
> return -ENODEV;
> }
>
> - clint_ipi_base = base + CLINT_IPI_OFF;
> - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> - clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {
This patch should come after patch 8 which introduces this DT binding
> + clint_ipi_base = NULL;
> + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
> + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
> + } else {
> + clint_ipi_base = base + CLINT_IPI_OFF;
> + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> + clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> + }
> clint_timer_freq = riscv_timebase;
>
> #ifdef CONFIG_RISCV_M_MODE
> @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
> goto fail_free_irq;
> }
>
> - riscv_set_ipi_ops(&clint_ipi_ops);
> - clint_clear_ipi();
> + if (clint_ipi_base) {
> + riscv_set_ipi_ops(&clint_ipi_ops);
> + clint_clear_ipi();
> + }
>
> return 0;
>
> @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
>
> TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
> TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
> +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-06-14 13:35 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-12 16:04 [RFC PATCH v1 00/10] RISC-V ACLINT Support Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-06-14 13:33 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Anup Patel
2021-06-14 13:33 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-06-13 9:33 ` Marc Zyngier
2021-06-13 12:28 ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-06-13 9:41 ` Marc Zyngier
2021-06-13 12:25 ` Anup Patel
2021-06-14 9:38 ` Marc Zyngier
2021-06-14 13:13 ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-06-14 13:34 ` Bin Meng [this message]
2021-06-12 16:04 ` [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-24 19:37 ` Rob Herring
2021-06-12 16:04 ` [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
2021-06-14 13:34 ` Bin Meng
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