From: Daniel Baluta <daniel.baluta@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Daniel Baluta <daniel.baluta@nxp.com>,
Devicetree List <devicetree@vger.kernel.org>,
Linux-ALSA <alsa-devel@alsa-project.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Timur Tabi <timur@kernel.org>, Rob Herring <robh@kernel.org>,
"S.j. Wang" <shengjiu.wang@nxp.com>,
"Angus Ainslie (Purism)" <angus@akkea.ca>,
Takashi Iwai <tiwai@suse.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Mark Brown <broonie@kernel.org>, dl-linux-imx <linux-imx@nxp.com>,
Viorel Suman <viorel.suman@nxp.com>,
Fabio Estevam <festevam@gmail.com>,
Mihai Serban <mihai.serban@gmail.com>,
Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [alsa-devel] [PATCH v2 1/7] ASoC: fsl_sai: Add registers definition for multiple datalines
Date: Mon, 29 Jul 2019 22:57:43 +0300 [thread overview]
Message-ID: <CAEnQRZDmnAmgUkRGv3V5S7b5EnYTd2BO5NFuME2CfGb1=nAHzQ@mail.gmail.com> (raw)
In-Reply-To: <20190729194214.GA20594@Asurada-Nvidia.nvidia.com>
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
> > SAI IP supports up to 8 data lines. The configuration of
> > supported number of data lines is decided at SoC integration
> > time.
> >
> > This patch adds definitions for all related data TX/RX registers:
> > * TDR0..7, Transmit data register
> > * TFR0..7, Transmit FIFO register
> > * RDR0..7, Receive data register
> > * RFR0..7, Receive FIFO register
> >
> > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
> > ---
> > sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------
> > sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++---
> > 2 files changed, 98 insertions(+), 14 deletions(-)
> >
> > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> > index 6d3c6c8d50ce..17b0aff4ee8b 100644
> > --- a/sound/soc/fsl/fsl_sai.c
> > +++ b/sound/soc/fsl/fsl_sai.c
>
> > @@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
> > case FSL_SAI_TCR3:
> > case FSL_SAI_TCR4:
> > case FSL_SAI_TCR5:
> > - case FSL_SAI_TFR:
> > + case FSL_SAI_TFR0:
> > + case FSL_SAI_TFR1:
> > + case FSL_SAI_TFR2:
> > + case FSL_SAI_TFR3:
> > + case FSL_SAI_TFR4:
> > + case FSL_SAI_TFR5:
> > + case FSL_SAI_TFR6:
> > + case FSL_SAI_TFR7:
> > case FSL_SAI_TMR:
> > case FSL_SAI_RCSR:
> > case FSL_SAI_RCR1:
>
> A tricky thing here is that those SAI instances on older SoC don't
> support multi data lines physically, while seemly having registers
> pre-defined. So your change doesn't sound doing anything wrong to
> them at all, I am still wondering if it is necessary to apply them
> to newer compatible only though, as for older compatibles of SAI,
> these registers would be useless and confusing if being exposed.
>
> What do you think?
Yes, I thought about this too. But, I tried to keep the code as short
as possible and technically it is not wrong. When 1 data line is supported
for example application will only care about TDR0, TFR0, etc.
next prev parent reply other threads:[~2019-07-29 19:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-28 19:24 [PATCH v2 0/7] Add support for new SAI IP version Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 1/7] ASoC: fsl_sai: Add registers definition for multiple datalines Daniel Baluta
2019-07-29 19:42 ` Nicolin Chen
2019-07-29 19:57 ` Daniel Baluta [this message]
2019-07-29 20:20 ` [alsa-devel] " Mark Brown
2019-07-30 7:59 ` Nicolin Chen
2019-08-06 11:15 ` Daniel Baluta
2019-08-07 1:12 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 2/7] ASoC: fsl_sai: Update Tx/Rx channel enable mask Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 3/7] ASoC: fsl_sai: Add support to enable multiple data lines Daniel Baluta
2019-07-29 20:21 ` Nicolin Chen
2019-08-06 15:23 ` Daniel Baluta
2019-08-07 1:14 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 4/7] ASoC: dt-bindings: Document dl-mask property Daniel Baluta
2019-07-29 20:15 ` Nicolin Chen
2019-07-29 20:27 ` Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 5/7] ASoC: fsl_sai: Add support for SAI new version Daniel Baluta
2019-07-28 19:24 ` [PATCH v2 6/7] ASoC: fsl_sai: Add support for imx7ulp/imx8mq Daniel Baluta
2019-07-30 8:05 ` Nicolin Chen
2019-07-28 19:24 ` [PATCH v2 7/7] ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ Daniel Baluta
2019-07-30 8:01 ` Nicolin Chen
2019-07-30 12:02 ` [alsa-devel] " Daniel Baluta
2019-07-30 12:04 ` Mark Brown
2019-07-30 12:10 ` Daniel Baluta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAEnQRZDmnAmgUkRGv3V5S7b5EnYTd2BO5NFuME2CfGb1=nAHzQ@mail.gmail.com' \
--to=daniel.baluta@gmail.com \
--cc=alsa-devel@alsa-project.org \
--cc=angus@akkea.ca \
--cc=broonie@kernel.org \
--cc=daniel.baluta@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=l.stach@pengutronix.de \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mihai.serban@gmail.com \
--cc=nicoleotsuka@gmail.com \
--cc=robh@kernel.org \
--cc=shengjiu.wang@nxp.com \
--cc=timur@kernel.org \
--cc=tiwai@suse.com \
--cc=viorel.suman@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).