From: Thor Thayer <tthayer.linux@gmail.com>
To: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: Thor Thayer <tthayer@altera.com>,
robherring2@gmail.com, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
rob@landley.net, linux@arm.linux.org.uk,
Dinh Nguyen <dinguyen@altera.com>,
dougthompson@xmission.com, grant.likely@linaro.org,
Borislav Petkov <bp@alien8.de>,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller
Date: Tue, 6 May 2014 13:34:36 -0500 [thread overview]
Message-ID: <CAF03EBfO9JELqJim10r7dJnmLH41i_VxZt_vnRKaOOO96eH_JA@mail.gmail.com> (raw)
In-Reply-To: <ba35254f-4ba5-4b2c-8056-cde5c693b0ff@CH1EHSMHS009.ehs.local>
Hi Sören
On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann
<soren.brinkmann@xilinx.com> wrote:
>
> Hi Thor,
>
> On Mon, 2014-05-05 at 05:52PM -0500, tthayer@altera.com wrote:
> > From: Thor Thayer <tthayer@altera.com>
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to the Altera SoC project. The "syscon" parameter
> > is included here because the SDRAM EDAC bits are shared with the SDRAM
> > configuration bits.
> > ---
> > v2: Changes to SoC SDRAM EDAC code.
> >
> > V3: Implement code suggestions for SDRAM EDAC code.
> >
> > Signed-off-by: Thor Thayer <tthayer@altera.com>
> > ---
> > .../bindings/arm/altera/socfpga-sdram.txt | 14 ++++++++++++++
> > arch/arm/boot/dts/socfpga.dtsi | 5 +++++
> > 2 files changed, 19 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
> > new file mode 100644
> > index 0000000..525cb76
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
> > @@ -0,0 +1,14 @@
> > +Altera SOCFPGA SDRAM Controller
> > +
> > +Required properties:
> > +- compatible : "altr,sdr-ctl", "syscon";
> > + Note that syscon is invoked for this device to support the FPGA
> > + bridge driver, EDAC driver and other devices that share the
> > + registers.
>
> This sounds like implementation specifics, which shouldn't be part of
> the bindings.
>
> Sören
>
I see your point and will remove. Thanks!
next prev parent reply other threads:[~2014-05-06 18:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-05 22:52 edac: altera: Add EDAC support for Altera SDRAM Controller tthayer
2014-05-05 22:52 ` [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller tthayer
2014-05-05 23:16 ` Sören Brinkmann
2014-05-06 18:34 ` Thor Thayer [this message]
2014-05-05 22:52 ` [PATCHv3 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC tthayer
2014-05-05 22:52 ` [PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM tthayer
2014-05-06 15:42 ` Dinh Nguyen
2014-05-06 21:00 ` Thor Thayer
2014-05-08 12:05 ` Borislav Petkov
2014-05-08 20:37 ` Thor Thayer
2014-05-09 13:52 ` Borislav Petkov
2014-05-09 20:31 ` Thor Thayer
2014-05-09 20:52 ` Borislav Petkov
2014-05-12 21:58 ` Thor Thayer
2014-05-08 22:44 ` Dinh Nguyen
2014-05-09 20:04 ` Thor Thayer
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