From: Rob Clark <robdclark@gmail.com>
To: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Cc: dri-devel <dri-devel@lists.freedesktop.org>,
"moderated list:DMA BUFFER SHARING FRAMEWORK"
<linaro-mm-sig@lists.linaro.org>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Christian König" <ckoenig.leichtzumerken@gmail.com>,
"Michel Dänzer" <michel@daenzer.net>,
"Pekka Paalanen" <ppaalanen@gmail.com>,
"Rob Clark" <robdclark@chromium.org>,
"David Airlie" <airlied@linux.ie>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
"Tian Tao" <tiantao6@hisilicon.com>,
"Steven Price" <steven.price@arm.com>,
"Melissa Wen" <mwen@igalia.com>,
"Luben Tuikov" <luben.tuikov@amd.com>,
"Boris Brezillon" <boris.brezillon@collabora.com>,
"Jack Zhang" <Jack.Zhang1@amd.com>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:DMA BUFFER SHARING FRAMEWORK"
<linux-media@vger.kernel.org>
Subject: Re: [PATCH v3 4/9] drm/scheduler: Add fence deadline support
Date: Wed, 22 Sep 2021 08:01:56 -0700 [thread overview]
Message-ID: <CAF6AEGupLaG2GuSvY0qerWD7sB6JAzDgyx_XP2eHYqy+Of5f0w@mail.gmail.com> (raw)
In-Reply-To: <ff396c19-c6ed-5f25-32df-c404bc8ea661@amd.com>
On Wed, Sep 22, 2021 at 7:31 AM Andrey Grodzovsky
<andrey.grodzovsky@amd.com> wrote:
>
>
> On 2021-09-21 11:32 p.m., Rob Clark wrote:
> > On Tue, Sep 21, 2021 at 7:18 PM Andrey Grodzovsky
> > <andrey.grodzovsky@amd.com> wrote:
> >>
> >> On 2021-09-21 4:47 p.m., Rob Clark wrote:
> >>> On Tue, Sep 21, 2021 at 1:09 PM Andrey Grodzovsky
> >>> <andrey.grodzovsky@amd.com> wrote:
> >>>> On 2021-09-03 2:47 p.m., Rob Clark wrote:
> >>>>
> >>>>> From: Rob Clark <robdclark@chromium.org>
> >>>>>
> >>>>> As the finished fence is the one that is exposed to userspace, and
> >>>>> therefore the one that other operations, like atomic update, would
> >>>>> block on, we need to propagate the deadline from from the finished
> >>>>> fence to the actual hw fence.
> >>>>>
> >>>>> v2: Split into drm_sched_fence_set_parent() (ckoenig)
> >>>>>
> >>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> >>>>> ---
> >>>>> drivers/gpu/drm/scheduler/sched_fence.c | 34 +++++++++++++++++++++++++
> >>>>> drivers/gpu/drm/scheduler/sched_main.c | 2 +-
> >>>>> include/drm/gpu_scheduler.h | 8 ++++++
> >>>>> 3 files changed, 43 insertions(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c
> >>>>> index bcea035cf4c6..4fc41a71d1c7 100644
> >>>>> --- a/drivers/gpu/drm/scheduler/sched_fence.c
> >>>>> +++ b/drivers/gpu/drm/scheduler/sched_fence.c
> >>>>> @@ -128,6 +128,30 @@ static void drm_sched_fence_release_finished(struct dma_fence *f)
> >>>>> dma_fence_put(&fence->scheduled);
> >>>>> }
> >>>>>
> >>>>> +static void drm_sched_fence_set_deadline_finished(struct dma_fence *f,
> >>>>> + ktime_t deadline)
> >>>>> +{
> >>>>> + struct drm_sched_fence *fence = to_drm_sched_fence(f);
> >>>>> + unsigned long flags;
> >>>>> +
> >>>>> + spin_lock_irqsave(&fence->lock, flags);
> >>>>> +
> >>>>> + /* If we already have an earlier deadline, keep it: */
> >>>>> + if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags) &&
> >>>>> + ktime_before(fence->deadline, deadline)) {
> >>>>> + spin_unlock_irqrestore(&fence->lock, flags);
> >>>>> + return;
> >>>>> + }
> >>>>> +
> >>>>> + fence->deadline = deadline;
> >>>>> + set_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags);
> >>>>> +
> >>>>> + spin_unlock_irqrestore(&fence->lock, flags);
> >>>>> +
> >>>>> + if (fence->parent)
> >>>>> + dma_fence_set_deadline(fence->parent, deadline);
> >>>>> +}
> >>>>> +
> >>>>> static const struct dma_fence_ops drm_sched_fence_ops_scheduled = {
> >>>>> .get_driver_name = drm_sched_fence_get_driver_name,
> >>>>> .get_timeline_name = drm_sched_fence_get_timeline_name,
> >>>>> @@ -138,6 +162,7 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = {
> >>>>> .get_driver_name = drm_sched_fence_get_driver_name,
> >>>>> .get_timeline_name = drm_sched_fence_get_timeline_name,
> >>>>> .release = drm_sched_fence_release_finished,
> >>>>> + .set_deadline = drm_sched_fence_set_deadline_finished,
> >>>>> };
> >>>>>
> >>>>> struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
> >>>>> @@ -152,6 +177,15 @@ struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
> >>>>> }
> >>>>> EXPORT_SYMBOL(to_drm_sched_fence);
> >>>>>
> >>>>> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
> >>>>> + struct dma_fence *fence)
> >>>>> +{
> >>>>> + s_fence->parent = dma_fence_get(fence);
> >>>>> + if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT,
> >>>>> + &s_fence->finished.flags))
> >>>>> + dma_fence_set_deadline(fence, s_fence->deadline);
> >>>> I believe above you should pass be s_fence->finished to
> >>>> dma_fence_set_deadline
> >>>> instead it fence which is the HW fence itself.
> >>> Hmm, unless this has changed recently with some patches I don't have,
> >>> s_fence->parent is the one signalled by hw, so it is the one we want
> >>> to set the deadline on
> >>>
> >>> BR,
> >>> -R
> >>
> >> No it didn't change. But then when exactly will
> >> drm_sched_fence_set_deadline_finished
> >> execute such that fence->parent != NULL ? In other words, I am not clear
> >> how propagation
> >> happens otherwise - if dma_fence_set_deadline is called with the HW
> >> fence then the assumption
> >> here is that driver provided driver specific
> >> dma_fence_ops.dma_fence_set_deadline callback executes
> >> but I was under impression that drm_sched_fence_set_deadline_finished is
> >> the one that propagates
> >> the deadline to the HW fence's callback and for it to execute
> >> dma_fence_set_deadline needs to be called
> >> with s_fence->finished.
> > Assuming I didn't screw up drm/msm conversion to scheduler,
> > &s_fence->finished is the one that will be returned to userspace.. and
> > later passed back to kernel for atomic commit (or to the compositor).
> > So it is the one that fence->set_deadline() will be called on. But
> > s_fence->parent is the actual hw fence that needs to know about the
> > deadline. Depending on whether or not the job has been written into
> > hw ringbuffer or not, there are two cases:
> >
> > 1) not scheduled yet, s_fence will store the deadline and propagate it
> > later once s_fence->parent is known
>
>
> And by later you mean the call to drm_sched_fence_set_parent
> after HW fence is returned ? If yes I think i get it now.
Yup :-)
BR,
-R
> Andrey
>
>
> > 2) already scheduled, in which case s_fence->finished.set_deadline
> > will propagate it directly to the real fence
> >
> > BR,
> > -R
> >
> >> Andrey
> >>
> >>
> >>
> >>>> Andrey
> >>>>
> >>>>
> >>>>> +}
> >>>>> +
> >>>>> struct drm_sched_fence *drm_sched_fence_alloc(struct drm_sched_entity *entity,
> >>>>> void *owner)
> >>>>> {
> >>>>> diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
> >>>>> index 595e47ff7d06..27bf0ac0625f 100644
> >>>>> --- a/drivers/gpu/drm/scheduler/sched_main.c
> >>>>> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> >>>>> @@ -978,7 +978,7 @@ static int drm_sched_main(void *param)
> >>>>> drm_sched_fence_scheduled(s_fence);
> >>>>>
> >>>>> if (!IS_ERR_OR_NULL(fence)) {
> >>>>> - s_fence->parent = dma_fence_get(fence);
> >>>>> + drm_sched_fence_set_parent(s_fence, fence);
> >>>>> r = dma_fence_add_callback(fence, &sched_job->cb,
> >>>>> drm_sched_job_done_cb);
> >>>>> if (r == -ENOENT)
> >>>>> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
> >>>>> index 7f77a455722c..158ddd662469 100644
> >>>>> --- a/include/drm/gpu_scheduler.h
> >>>>> +++ b/include/drm/gpu_scheduler.h
> >>>>> @@ -238,6 +238,12 @@ struct drm_sched_fence {
> >>>>> */
> >>>>> struct dma_fence finished;
> >>>>>
> >>>>> + /**
> >>>>> + * @deadline: deadline set on &drm_sched_fence.finished which
> >>>>> + * potentially needs to be propagated to &drm_sched_fence.parent
> >>>>> + */
> >>>>> + ktime_t deadline;
> >>>>> +
> >>>>> /**
> >>>>> * @parent: the fence returned by &drm_sched_backend_ops.run_job
> >>>>> * when scheduling the job on hardware. We signal the
> >>>>> @@ -505,6 +511,8 @@ void drm_sched_entity_set_priority(struct drm_sched_entity *entity,
> >>>>> enum drm_sched_priority priority);
> >>>>> bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
> >>>>>
> >>>>> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
> >>>>> + struct dma_fence *fence);
> >>>>> struct drm_sched_fence *drm_sched_fence_alloc(
> >>>>> struct drm_sched_entity *s_entity, void *owner);
> >>>>> void drm_sched_fence_init(struct drm_sched_fence *fence,
next prev parent reply other threads:[~2021-09-22 14:57 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 18:47 [PATCH v3 0/9] dma-fence: Deadline awareness Rob Clark
2021-09-03 18:47 ` [PATCH v3 1/9] dma-fence: Add deadline awareness Rob Clark
2021-09-08 17:55 ` Daniel Vetter
2021-09-03 18:47 ` [PATCH v3 2/9] drm/vblank: Add helper to get next vblank time Rob Clark
2021-09-03 18:47 ` [PATCH v3 3/9] drm/atomic-helper: Set fence deadline for vblank Rob Clark
2021-09-03 18:47 ` [PATCH v3 4/9] drm/scheduler: Add fence deadline support Rob Clark
2021-09-08 17:45 ` Daniel Vetter
2021-09-09 6:22 ` Christian König
2021-09-14 13:38 ` Daniel Vetter
2021-09-21 15:57 ` Rob Clark
2021-09-21 16:35 ` Rob Clark
2021-09-21 16:45 ` Christian König
2021-09-21 20:09 ` Andrey Grodzovsky
2021-09-21 20:47 ` Rob Clark
2021-09-22 2:18 ` Andrey Grodzovsky
2021-09-22 3:32 ` Rob Clark
2021-09-22 14:31 ` Andrey Grodzovsky
2021-09-22 15:01 ` Rob Clark [this message]
2021-09-03 18:47 ` [PATCH v3 5/9] drm/msm: Add deadline based boost support Rob Clark
2021-09-08 17:48 ` Daniel Vetter
2021-09-08 17:57 ` Rob Clark
2021-09-03 18:47 ` [PATCH v3 6/9] dma-buf/fence-array: Add fence deadline support Rob Clark
2021-09-08 18:00 ` Daniel Vetter
2021-09-09 6:55 ` Christian König
2021-09-03 18:47 ` [PATCH v3 7/9] dma-buf/fence-chain: " Rob Clark
2021-09-08 17:54 ` Daniel Vetter
2021-09-08 18:19 ` Rob Clark
2021-09-08 18:45 ` Daniel Vetter
2021-09-09 6:31 ` Christian König
2021-09-03 18:47 ` [PATCH v3 8/9] dma-buf/sync_file: Add SET_DEADLINE ioctl Rob Clark
2021-09-08 17:50 ` Daniel Vetter
2021-09-08 18:23 ` Rob Clark
2021-09-08 18:49 ` Daniel Vetter
2021-09-08 19:40 ` Rob Clark
2021-09-08 21:10 ` Daniel Vetter
2021-09-21 18:08 ` Rob Clark
2021-09-27 8:42 ` Pekka Paalanen
2021-09-27 8:53 ` Christian König
2021-09-27 14:36 ` Rob Clark
2021-09-28 7:57 ` Pekka Paalanen
2021-09-03 18:48 ` [PATCH v3 9/9] dma-buf/sw_sync: Add fence deadline support Rob Clark
2021-09-09 16:16 ` [PATCH v3 0/9] dma-fence: Deadline awareness Simon Ser
2021-09-09 16:35 ` Rob Clark
2021-09-09 16:42 ` Simon Ser
2021-09-09 17:08 ` Rob Clark
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAF6AEGupLaG2GuSvY0qerWD7sB6JAzDgyx_XP2eHYqy+Of5f0w@mail.gmail.com \
--to=robdclark@gmail.com \
--cc=Jack.Zhang1@amd.com \
--cc=airlied@linux.ie \
--cc=andrey.grodzovsky@amd.com \
--cc=boris.brezillon@collabora.com \
--cc=christian.koenig@amd.com \
--cc=ckoenig.leichtzumerken@gmail.com \
--cc=daniel@ffwll.ch \
--cc=dri-devel@lists.freedesktop.org \
--cc=linaro-mm-sig@lists.linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=luben.tuikov@amd.com \
--cc=michel@daenzer.net \
--cc=mwen@igalia.com \
--cc=ppaalanen@gmail.com \
--cc=robdclark@chromium.org \
--cc=steven.price@arm.com \
--cc=sumit.semwal@linaro.org \
--cc=tiantao6@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).