[PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Sumit Garg]

With pseudo NMIs support available its possible to configure SGIs to be
triggered as pseudo NMIs running in NMI context. And kernel features
such as:
- NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
  stuck in hard lockup using magic SYSRQ.
- kgdb relies on NMI support to round up CPUs which are stuck in hard
  lockup state with interrupts disabled.

This patch-set adds framework to turn an IPI as NMI which can be triggered
as a pseudo NMI which in turn invokes registered NMI handlers.

After this patch-set we should be able to get a backtrace for a CPU
stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
testcase run on Developerbox:

$ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT

NMI backtrace:
==============

# Issue Magic SysRq to dump backtrace

[  376.894502] NMI backtrace for cpu 8
[  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
[  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
[  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
[  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
[  376.894520] lr : lkdtm_do_action+0x24/0x30
[  376.894524] sp : ffff800012cebd20
[  376.894527] pmr_save: 00000060
[  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
[  376.894540] x27: 0000000000000000 x26: 0000000000000000
[  376.894550] x25: 000000000000001a x24: ffff800012cebe40
[  376.894560] x23: 000000000000000b x22: ffff800010fc5040
[  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
[  376.894579] x19: 000000000000001b x18: 0000000000000010
[  376.894588] x17: 0000000000000000 x16: 0000000000000000
[  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
[  376.894613] x13: 0000000000000000 x12: 0000000000000000
[  376.894622] x11: 0000000000000007 x10: 00000000000009c0
[  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
[  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
[  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
[  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
[  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
[  376.894679] Call trace:
[  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
[  376.894686]  direct_entry+0x124/0x1c0
[  376.894689]  full_proxy_write+0x60/0xb0
[  376.894693]  vfs_write+0xf0/0x230
[  376.894696]  ksys_write+0x6c/0xf8
[  376.894699]  __arm64_sys_write+0x1c/0x28
[  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
[  376.894707]  do_el0_svc+0x24/0x90
[  376.894710]  el0_sync_handler+0x180/0x2f8
[  376.894713]  el0_sync+0x158/0x180

KGDB:
=====

# Enter kdb via Magic SysRq

[6]kdb> btc
btc: cpu status: Currently on cpu 6
Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
<snip>
Stack traceback for pid 555
0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
Call trace:
 dump_backtrace+0x0/0x1a0
 show_stack+0x18/0x28
 dump_stack+0xc0/0x11c
 kgdb_cpu_enter+0x648/0x660
 kgdb_nmicallback+0xa0/0xa8
 ipi_kgdb_nmicallback+0x24/0x30
 ipi_nmi_handler+0x48/0x60
 handle_percpu_devid_fasteoi_ipi+0x74/0x88
 generic_handle_irq+0x30/0x48
 handle_domain_nmi+0x48/0x80
 gic_handle_irq+0x18c/0x34c
 el1_irq+0xcc/0x180 
 lkdtm_HARDLOCKUP+0x8/0x18
 direct_entry+0x124/0x1c0
 full_proxy_write+0x60/0xb0
 vfs_write+0xf0/0x230
 ksys_write+0x6c/0xf8
 __arm64_sys_write+0x1c/0x28
 el0_svc_common.constprop.0+0x74/0x1f0
 do_el0_svc+0x24/0x90
 el0_sync_handler+0x180/0x2f8
 el0_sync+0x158/0x180
<snip>

Changes in v7:
- Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
  mechanism to arch specific code.
- Addressed other misc comments from Daniel.

Changes in v6:
- Two new patches: #4 and #6 which adds runtime fallback framework for
  sysrq backtrace and kgdb roundup features.
- Reversed order of NMI backtrace and kgdb roundup feaure patches.
- Addressed other misc. comments from Marc.
- I haven't picked any tags from v5 since I think there is major rework
  involved. Masayoshi, could you please confirm if these features still
  work for you?

Changes in v5:
- Rebased to head of upstream master.
- Remove redundant invocation of ipi_nmi_setup().
- Addressed misc. comments.

Changes in v4:
- Move IPI NMI framework to a separate file.
- Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
- Add NMI backtrace support leveraged via magic SYSRQ.

Changes in v3:
- Rebased to Marc's latest IPIs patch-set [1].

[1] https://lkml.org/lkml/2020/9/1/603

Changes since RFC version [1]:
- Switch to use generic interrupt framework to turn an IPI as NMI.
- Dependent on Marc's patch-set [2] which turns IPIs into normal
  interrupts.
- Addressed misc. comments from Doug on patch #4.
- Posted kgdb NMI printk() fixup separately which has evolved since
  to be solved using different approach via changing kgdb interception
  of printk() in common printk() code (see patch [3]).

[1] https://lkml.org/lkml/2020/4/24/328
[2] https://lkml.org/lkml/2020/5/19/710
[3] https://lkml.org/lkml/2020/5/20/418

Sumit Garg (7):
  arm64: Add framework to turn IPI as NMI
  irqchip/gic-v3: Enable support for SGIs to act as NMIs
  arm64: smp: Assign and setup an IPI as NMI
  nmi: backtrace: Allow runtime arch specific override
  arm64: ipi_nmi: Add support for NMI backtrace
  kgdb: Expose default CPUs roundup fallback mechanism
  arm64: kgdb: Roundup cpus using IPI as NMI

 arch/arm/include/asm/irq.h       |  2 +-
 arch/arm/kernel/smp.c            |  3 +-
 arch/arm64/include/asm/irq.h     |  6 +++
 arch/arm64/include/asm/nmi.h     | 17 ++++++++
 arch/arm64/kernel/Makefile       |  2 +-
 arch/arm64/kernel/ipi_nmi.c      | 84 ++++++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/kgdb.c         | 18 +++++++++
 arch/arm64/kernel/smp.c          |  8 ++++
 arch/mips/include/asm/irq.h      |  2 +-
 arch/mips/kernel/process.c       |  3 +-
 arch/powerpc/include/asm/nmi.h   |  2 +-
 arch/powerpc/kernel/stacktrace.c |  3 +-
 arch/sparc/include/asm/irq_64.h  |  2 +-
 arch/sparc/kernel/process_64.c   |  4 +-
 arch/x86/include/asm/irq.h       |  2 +-
 arch/x86/kernel/apic/hw_nmi.c    |  3 +-
 drivers/irqchip/irq-gic-v3.c     | 29 ++++++++++----
 include/linux/kgdb.h             | 12 ++++++
 include/linux/nmi.h              | 12 ++----
 kernel/debug/debug_core.c        |  8 +++-
 20 files changed, 194 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm64/include/asm/nmi.h
 create mode 100644 arch/arm64/kernel/ipi_nmi.c

-- 
2.7.4

[PATCH v7 1/7] arm64: Add framework to turn IPI as NMI

[Sumit Garg]

Introduce framework to turn an IPI as NMI using pseudo NMIs. The main
motivation for this feature is to have an IPI that can be leveraged to
invoke NMI functions on other CPUs.

And current prospective users are NMI backtrace and KGDB CPUs round-up
whose support is added via future patches.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm64/include/asm/nmi.h | 17 ++++++++++++
 arch/arm64/kernel/Makefile   |  2 +-
 arch/arm64/kernel/ipi_nmi.c  | 65 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/nmi.h
 create mode 100644 arch/arm64/kernel/ipi_nmi.c

diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h
new file mode 100644
index 0000000..4cd14b6
--- /dev/null
+++ b/arch/arm64/include/asm/nmi.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_NMI_H
+#define __ASM_NMI_H
+
+#ifndef __ASSEMBLER__
+
+#include <linux/cpumask.h>
+
+extern bool arm64_supports_nmi(void);
+extern void arm64_send_nmi(cpumask_t *mask);
+
+void set_smp_dynamic_ipi(int ipi);
+void dynamic_ipi_setup(int cpu);
+void dynamic_ipi_teardown(int cpu);
+
+#endif /* !__ASSEMBLER__ */
+#endif
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index bbaf0bc..525a1e0 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -17,7 +17,7 @@ obj-y			:= debug-monitors.o entry.o irq.o fpsimd.o		\
 			   return_address.o cpuinfo.o cpu_errata.o		\
 			   cpufeature.o alternative.o cacheinfo.o		\
 			   smp.o smp_spin_table.o topology.o smccc-call.o	\
-			   syscall.o proton-pack.o
+			   syscall.o proton-pack.o ipi_nmi.o
 
 targets			+= efi-entry.o
 
diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
new file mode 100644
index 0000000..a945dcf
--- /dev/null
+++ b/arch/arm64/kernel/ipi_nmi.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * NMI support for IPIs
+ *
+ * Copyright (C) 2020 Linaro Limited
+ * Author: Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+
+#include <asm/nmi.h>
+
+static struct irq_desc *ipi_nmi_desc __read_mostly;
+static int ipi_nmi_id __read_mostly;
+
+bool arm64_supports_nmi(void)
+{
+	if (ipi_nmi_desc)
+		return true;
+
+	return false;
+}
+
+void arm64_send_nmi(cpumask_t *mask)
+{
+	if (WARN_ON_ONCE(!ipi_nmi_desc))
+		return;
+
+	__ipi_send_mask(ipi_nmi_desc, mask);
+}
+
+static irqreturn_t ipi_nmi_handler(int irq, void *data)
+{
+	/* nop, NMI handlers for special features can be added here. */
+
+	return IRQ_NONE;
+}
+
+void dynamic_ipi_setup(int cpu)
+{
+	if (!ipi_nmi_desc)
+		return;
+
+	if (!prepare_percpu_nmi(ipi_nmi_id))
+		enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE);
+}
+
+void dynamic_ipi_teardown(int cpu)
+{
+	if (!ipi_nmi_desc)
+		return;
+
+	disable_percpu_nmi(ipi_nmi_id);
+	teardown_percpu_nmi(ipi_nmi_id);
+}
+
+void __init set_smp_dynamic_ipi(int ipi)
+{
+	if (!request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number)) {
+		ipi_nmi_desc = irq_to_desc(ipi);
+		ipi_nmi_id = ipi;
+	}
+}
-- 
2.7.4

[PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs

[Sumit Garg]

Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a
special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
handler update in case of SGIs.

Also, enable NMI support prior to gic_smp_init() as allocation of SGIs
as IRQs/NMIs happen as part of this routine.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++--------
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 16fecc0..7010ae2 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d)
 static int gic_irq_nmi_setup(struct irq_data *d)
 {
 	struct irq_desc *desc = irq_to_desc(d->irq);
+	u32 idx;
 
 	if (!gic_supports_nmi())
 		return -EINVAL;
@@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d)
 		return -EINVAL;
 
 	/* desc lock should already be held */
-	if (gic_irq_in_rdist(d)) {
-		u32 idx = gic_get_ppi_index(d);
+	switch (get_intid_range(d)) {
+	case SGI_RANGE:
+		break;
+	case PPI_RANGE:
+	case EPPI_RANGE:
+		idx = gic_get_ppi_index(d);
 
 		/* Setting up PPI as NMI, only switch handler for first NMI */
 		if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
 			refcount_set(&ppi_nmi_refs[idx], 1);
 			desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
 		}
-	} else {
+		break;
+	default:
 		desc->handle_irq = handle_fasteoi_nmi;
+		break;
 	}
 
 	gic_irq_set_prio(d, GICD_INT_NMI_PRI);
@@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d)
 static void gic_irq_nmi_teardown(struct irq_data *d)
 {
 	struct irq_desc *desc = irq_to_desc(d->irq);
+	u32 idx;
 
 	if (WARN_ON(!gic_supports_nmi()))
 		return;
@@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
 		return;
 
 	/* desc lock should already be held */
-	if (gic_irq_in_rdist(d)) {
-		u32 idx = gic_get_ppi_index(d);
+	switch (get_intid_range(d)) {
+	case SGI_RANGE:
+		break;
+	case PPI_RANGE:
+	case EPPI_RANGE:
+		idx = gic_get_ppi_index(d);
 
 		/* Tearing down NMI, only switch handler for last NMI */
 		if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
 			desc->handle_irq = handle_percpu_devid_irq;
-	} else {
+		break;
+	default:
 		desc->handle_irq = handle_fasteoi_irq;
+		break;
 	}
 
 	gic_irq_set_prio(d, GICD_INT_DEF_PRI);
@@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
 
 	gic_dist_init();
 	gic_cpu_init();
+	gic_enable_nmi_support();
 	gic_smp_init();
 	gic_cpu_pm_init();
 
@@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base,
 			gicv2m_init(handle, gic_data.domain);
 	}
 
-	gic_enable_nmi_support();
-
 	return 0;
 
 out_free:
-- 
2.7.4

[PATCH v7 3/7] arm64: smp: Assign and setup an IPI as NMI

[Sumit Garg]

Assign an unused IPI which can be turned as NMI using ipi_nmi framework.
Also, invoke corresponding dynamic IPI setup/teardown APIs.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm64/kernel/smp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 82e75fc..2e118e2 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -43,6 +43,7 @@
 #include <asm/daifflags.h>
 #include <asm/kvm_mmu.h>
 #include <asm/mmu_context.h>
+#include <asm/nmi.h>
 #include <asm/numa.h>
 #include <asm/processor.h>
 #include <asm/smp_plat.h>
@@ -962,6 +963,8 @@ static void ipi_setup(int cpu)
 
 	for (i = 0; i < nr_ipi; i++)
 		enable_percpu_irq(ipi_irq_base + i, 0);
+
+	dynamic_ipi_setup(cpu);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -974,6 +977,8 @@ static void ipi_teardown(int cpu)
 
 	for (i = 0; i < nr_ipi; i++)
 		disable_percpu_irq(ipi_irq_base + i);
+
+	dynamic_ipi_teardown(cpu);
 }
 #endif
 
@@ -995,6 +1000,9 @@ void __init set_smp_ipi_range(int ipi_base, int n)
 		irq_set_status_flags(ipi_base + i, IRQ_HIDDEN);
 	}
 
+	if (n > nr_ipi)
+		set_smp_dynamic_ipi(ipi_base + nr_ipi);
+
 	ipi_irq_base = ipi_base;
 
 	/* Setup the boot CPU immediately */
-- 
2.7.4

[PATCH v7 4/7] nmi: backtrace: Allow runtime arch specific override

[Sumit Garg]

Add a boolean return to arch_trigger_cpumask_backtrace() to support a
use-case where a particular architecture detects at runtime if it supports
NMI backtrace or it would like to fallback to default implementation using
SMP cross-calls.

Currently such an architecture example is arm64 supporting pseudo NMIs
feature which is only available on platforms which have support for GICv3
or later version.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm/include/asm/irq.h       |  2 +-
 arch/arm/kernel/smp.c            |  3 ++-
 arch/mips/include/asm/irq.h      |  2 +-
 arch/mips/kernel/process.c       |  3 ++-
 arch/powerpc/include/asm/nmi.h   |  2 +-
 arch/powerpc/kernel/stacktrace.c |  3 ++-
 arch/sparc/include/asm/irq_64.h  |  2 +-
 arch/sparc/kernel/process_64.c   |  4 +++-
 arch/x86/include/asm/irq.h       |  2 +-
 arch/x86/kernel/apic/hw_nmi.c    |  3 ++-
 include/linux/nmi.h              | 12 ++++--------
 11 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 46d4114..54b0180 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -31,7 +31,7 @@ void handle_IRQ(unsigned int, struct pt_regs *);
 void init_IRQ(void);
 
 #ifdef CONFIG_SMP
-extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
+extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
 					   bool exclude_self);
 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 48099c6e..bb20a43 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -856,7 +856,8 @@ static void raise_nmi(cpumask_t *mask)
 	__ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask);
 }
 
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 {
 	nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi);
+	return true;
 }
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index c5d3517..34f3b42 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -78,7 +78,7 @@ extern int cp0_fdc_irq;
 
 extern int get_c0_fdc_int(void);
 
-void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
+bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
 				    bool exclude_self);
 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
 
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 75ebd8d..d19e672 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -735,9 +735,10 @@ static void raise_backtrace(cpumask_t *mask)
 	}
 }
 
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 {
 	nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
+	return true;
 }
 
 int mips_get_process_fp_mode(struct task_struct *task)
diff --git a/arch/powerpc/include/asm/nmi.h b/arch/powerpc/include/asm/nmi.h
index 84b4cfe..a5eb3e2 100644
--- a/arch/powerpc/include/asm/nmi.h
+++ b/arch/powerpc/include/asm/nmi.h
@@ -9,7 +9,7 @@ static inline void arch_touch_nmi_watchdog(void) {}
 #endif
 
 #if defined(CONFIG_NMI_IPI) && defined(CONFIG_STACKTRACE)
-extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
+extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
 					   bool exclude_self);
 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
 #endif
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
index b644065..22b112a 100644
--- a/arch/powerpc/kernel/stacktrace.c
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -264,8 +264,9 @@ static void raise_backtrace_ipi(cpumask_t *mask)
 	}
 }
 
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 {
 	nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace_ipi);
+	return true;
 }
 #endif /* defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_NMI_IPI) */
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index 4d748e9..35c01ff 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -87,7 +87,7 @@ static inline unsigned long get_softint(void)
 	return retval;
 }
 
-void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
+bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
 				    bool exclude_self);
 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
 
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index a75093b..9182001 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -248,7 +248,7 @@ static void __global_reg_poll(struct global_reg_snapshot *gp)
 	}
 }
 
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 {
 	struct thread_info *tp = current_thread_info();
 	struct pt_regs *regs = get_irq_regs();
@@ -303,6 +303,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 	memset(global_cpu_snapshot, 0, sizeof(global_cpu_snapshot));
 
 	spin_unlock_irqrestore(&global_cpu_snapshot_lock, flags);
+
+	return true;
 }
 
 #ifdef CONFIG_MAGIC_SYSRQ
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 528c8a7..b7668e0 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -47,7 +47,7 @@ extern void init_ISA_irqs(void);
 extern void __init init_IRQ(void);
 
 #ifdef CONFIG_X86_LOCAL_APIC
-void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
+bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
 				    bool exclude_self);
 
 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 34a992e..e7dcd28 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -34,10 +34,11 @@ static void nmi_raise_cpu_backtrace(cpumask_t *mask)
 	apic->send_IPI_mask(mask, NMI_VECTOR);
 }
 
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 {
 	nmi_trigger_cpumask_backtrace(mask, exclude_self,
 				      nmi_raise_cpu_backtrace);
+	return true;
 }
 
 static int nmi_cpu_backtrace_handler(unsigned int cmd, struct pt_regs *regs)
diff --git a/include/linux/nmi.h b/include/linux/nmi.h
index 750c7f3..cedbfc1 100644
--- a/include/linux/nmi.h
+++ b/include/linux/nmi.h
@@ -143,26 +143,22 @@ static inline void touch_nmi_watchdog(void)
 #ifdef arch_trigger_cpumask_backtrace
 static inline bool trigger_all_cpu_backtrace(void)
 {
-	arch_trigger_cpumask_backtrace(cpu_online_mask, false);
-	return true;
+	return arch_trigger_cpumask_backtrace(cpu_online_mask, false);
 }
 
 static inline bool trigger_allbutself_cpu_backtrace(void)
 {
-	arch_trigger_cpumask_backtrace(cpu_online_mask, true);
-	return true;
+	return arch_trigger_cpumask_backtrace(cpu_online_mask, true);
 }
 
 static inline bool trigger_cpumask_backtrace(struct cpumask *mask)
 {
-	arch_trigger_cpumask_backtrace(mask, false);
-	return true;
+	return arch_trigger_cpumask_backtrace(mask, false);
 }
 
 static inline bool trigger_single_cpu_backtrace(int cpu)
 {
-	arch_trigger_cpumask_backtrace(cpumask_of(cpu), false);
-	return true;
+	return arch_trigger_cpumask_backtrace(cpumask_of(cpu), false);
 }
 
 /* generic implementation */
-- 
2.7.4

[PATCH v7 5/7] arm64: ipi_nmi: Add support for NMI backtrace

[Sumit Garg]

Enable NMI backtrace support on arm64 using IPI turned as an NMI
leveraging pseudo NMIs support. It is now possible for users to get a
backtrace of a CPU stuck in hard-lockup using magic SYSRQ.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm64/include/asm/irq.h |  6 ++++++
 arch/arm64/kernel/ipi_nmi.c  | 18 ++++++++++++++++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
index b2b0c64..ef018a8 100644
--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
@@ -6,6 +6,12 @@
 
 #include <asm-generic/irq.h>
 
+#ifdef CONFIG_SMP
+extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
+					   bool exclude_self);
+#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
+#endif
+
 struct pt_regs;
 
 static inline int nr_legacy_irqs(void)
diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
index a945dcf..597dcf7 100644
--- a/arch/arm64/kernel/ipi_nmi.c
+++ b/arch/arm64/kernel/ipi_nmi.c
@@ -8,6 +8,7 @@
 
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/nmi.h>
 #include <linux/smp.h>
 
 #include <asm/nmi.h>
@@ -31,11 +32,24 @@ void arm64_send_nmi(cpumask_t *mask)
 	__ipi_send_mask(ipi_nmi_desc, mask);
 }
 
+bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
+{
+	if (!ipi_nmi_desc)
+		return false;
+
+	nmi_trigger_cpumask_backtrace(mask, exclude_self, arm64_send_nmi);
+
+	return true;
+}
+
 static irqreturn_t ipi_nmi_handler(int irq, void *data)
 {
-	/* nop, NMI handlers for special features can be added here. */
+	irqreturn_t ret = IRQ_NONE;
+
+	if (nmi_cpu_backtrace(get_irq_regs()))
+		ret = IRQ_HANDLED;
 
-	return IRQ_NONE;
+	return ret;
 }
 
 void dynamic_ipi_setup(int cpu)
-- 
2.7.4

[PATCH v7 6/7] kgdb: Expose default CPUs roundup fallback mechanism

[Sumit Garg]

Add a new API kgdb_smp_call_nmi_hook() to expose default CPUs roundup
mechanism to a particular archichecture as a runtime fallback if it
detects to not support NMI roundup.

Currently such an architecture example is arm64 supporting pseudo NMIs
feature which is only available on platforms which have support for GICv3
or later version.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 include/linux/kgdb.h      | 12 ++++++++++++
 kernel/debug/debug_core.c |  8 +++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h
index 0d6cf64..4190f13 100644
--- a/include/linux/kgdb.h
+++ b/include/linux/kgdb.h
@@ -200,6 +200,18 @@ kgdb_arch_handle_qxfer_pkt(char *remcom_in_buffer,
 extern void kgdb_call_nmi_hook(void *ignored);
 
 /**
+ *	kgdb_smp_call_nmi_hook - Provide default fallback mechanism to
+ *				 round-up CPUs
+ *
+ *	If you're using the default implementation of kgdb_roundup_cpus()
+ *	this function will be called.  And if an arch detects at runtime to
+ *	not support NMI based roundup then it can fallback to default
+ *	mechanism using this API.
+ */
+
+extern void kgdb_smp_call_nmi_hook(void);
+
+/**
  *	kgdb_roundup_cpus - Get other CPUs into a holding pattern
  *
  *	On SMP systems, we need to get the attention of the other CPUs
diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c
index 1e75a89..ae785d8 100644
--- a/kernel/debug/debug_core.c
+++ b/kernel/debug/debug_core.c
@@ -241,7 +241,7 @@ void __weak kgdb_call_nmi_hook(void *ignored)
 }
 NOKPROBE_SYMBOL(kgdb_call_nmi_hook);
 
-void __weak kgdb_roundup_cpus(void)
+void kgdb_smp_call_nmi_hook(void)
 {
 	call_single_data_t *csd;
 	int this_cpu = raw_smp_processor_id();
@@ -273,6 +273,12 @@ void __weak kgdb_roundup_cpus(void)
 			kgdb_info[cpu].rounding_up = false;
 	}
 }
+NOKPROBE_SYMBOL(kgdb_smp_call_nmi_hook);
+
+void __weak kgdb_roundup_cpus(void)
+{
+	kgdb_smp_call_nmi_hook();
+}
 NOKPROBE_SYMBOL(kgdb_roundup_cpus);
 
 #endif
-- 
2.7.4

[PATCH v7 7/7] arm64: kgdb: Roundup cpus using IPI as NMI

[Sumit Garg]

arm64 platforms with GICv3 or later supports pseudo NMIs which can be
leveraged to roundup CPUs which are stuck in hard lockup state with
interrupts disabled that wouldn't be possible with a normal IPI.

So instead switch to roundup CPUs using IPI turned as NMI. And in
case a particular arm64 platform doesn't supports pseudo NMIs,
it will switch back to default kgdb CPUs roundup mechanism.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
 arch/arm64/kernel/ipi_nmi.c |  5 +++++
 arch/arm64/kernel/kgdb.c    | 18 ++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
index 597dcf7..898d69c 100644
--- a/arch/arm64/kernel/ipi_nmi.c
+++ b/arch/arm64/kernel/ipi_nmi.c
@@ -8,6 +8,7 @@
 
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/kgdb.h>
 #include <linux/nmi.h>
 #include <linux/smp.h>
 
@@ -45,10 +46,14 @@ bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 static irqreturn_t ipi_nmi_handler(int irq, void *data)
 {
 	irqreturn_t ret = IRQ_NONE;
+	unsigned int cpu = smp_processor_id();
 
 	if (nmi_cpu_backtrace(get_irq_regs()))
 		ret = IRQ_HANDLED;
 
+	if (!kgdb_nmicallback(cpu, get_irq_regs()))
+		ret = IRQ_HANDLED;
+
 	return ret;
 }
 
diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
index 1a157ca3..371b176 100644
--- a/arch/arm64/kernel/kgdb.c
+++ b/arch/arm64/kernel/kgdb.c
@@ -17,6 +17,7 @@
 
 #include <asm/debug-monitors.h>
 #include <asm/insn.h>
+#include <asm/nmi.h>
 #include <asm/traps.h>
 
 struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
@@ -353,3 +354,20 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
 	return aarch64_insn_write((void *)bpt->bpt_addr,
 			*(u32 *)bpt->saved_instr);
 }
+
+void kgdb_roundup_cpus(void)
+{
+	struct cpumask mask;
+
+	if (!arm64_supports_nmi()) {
+		kgdb_smp_call_nmi_hook();
+		return;
+	}
+
+	cpumask_copy(&mask, cpu_online_mask);
+	cpumask_clear_cpu(raw_smp_processor_id(), &mask);
+	if (cpumask_empty(&mask))
+		return;
+
+	arm64_send_nmi(&mask);
+}
-- 
2.7.4

Re: [PATCH v7 1/7] arm64: Add framework to turn IPI as NMI

[Masayoshi Mizuma]

On Mon, Nov 02, 2020 at 05:14:41PM +0530, Sumit Garg wrote:
> Introduce framework to turn an IPI as NMI using pseudo NMIs. The main
> motivation for this feature is to have an IPI that can be leveraged to
> invoke NMI functions on other CPUs.
> 
> And current prospective users are NMI backtrace and KGDB CPUs round-up
> whose support is added via future patches.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  arch/arm64/include/asm/nmi.h | 17 ++++++++++++
>  arch/arm64/kernel/Makefile   |  2 +-
>  arch/arm64/kernel/ipi_nmi.c  | 65 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 83 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm64/include/asm/nmi.h
>  create mode 100644 arch/arm64/kernel/ipi_nmi.c
> 
> diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h
> new file mode 100644
> index 0000000..4cd14b6
> --- /dev/null
> +++ b/arch/arm64/include/asm/nmi.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_NMI_H
> +#define __ASM_NMI_H
> +
> +#ifndef __ASSEMBLER__
> +
> +#include <linux/cpumask.h>
> +
> +extern bool arm64_supports_nmi(void);
> +extern void arm64_send_nmi(cpumask_t *mask);
> +
> +void set_smp_dynamic_ipi(int ipi);
> +void dynamic_ipi_setup(int cpu);
> +void dynamic_ipi_teardown(int cpu);
> +
> +#endif /* !__ASSEMBLER__ */
> +#endif
> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
> index bbaf0bc..525a1e0 100644
> --- a/arch/arm64/kernel/Makefile
> +++ b/arch/arm64/kernel/Makefile
> @@ -17,7 +17,7 @@ obj-y			:= debug-monitors.o entry.o irq.o fpsimd.o		\
>  			   return_address.o cpuinfo.o cpu_errata.o		\
>  			   cpufeature.o alternative.o cacheinfo.o		\
>  			   smp.o smp_spin_table.o topology.o smccc-call.o	\
> -			   syscall.o proton-pack.o
> +			   syscall.o proton-pack.o ipi_nmi.o
>  
>  targets			+= efi-entry.o
>  
> diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
> new file mode 100644
> index 0000000..a945dcf
> --- /dev/null
> +++ b/arch/arm64/kernel/ipi_nmi.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * NMI support for IPIs
> + *
> + * Copyright (C) 2020 Linaro Limited
> + * Author: Sumit Garg <sumit.garg@linaro.org>
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/smp.h>
> +
> +#include <asm/nmi.h>
> +
> +static struct irq_desc *ipi_nmi_desc __read_mostly;
> +static int ipi_nmi_id __read_mostly;
> +
> +bool arm64_supports_nmi(void)
> +{
> +	if (ipi_nmi_desc)
> +		return true;
> +
> +	return false;
> +}
> +
> +void arm64_send_nmi(cpumask_t *mask)
> +{
> +	if (WARN_ON_ONCE(!ipi_nmi_desc))
> +		return;
> +
> +	__ipi_send_mask(ipi_nmi_desc, mask);
> +}
> +
> +static irqreturn_t ipi_nmi_handler(int irq, void *data)
> +{
> +	/* nop, NMI handlers for special features can be added here. */
> +
> +	return IRQ_NONE;
> +}
> +

> +void dynamic_ipi_setup(int cpu)

cpu isn't used here, so void is better?

void dynamic_ipi_setup(void)

> +{
> +	if (!ipi_nmi_desc)
> +		return;
> +
> +	if (!prepare_percpu_nmi(ipi_nmi_id))
> +		enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE);
> +}
> +

> +void dynamic_ipi_teardown(int cpu)

Same as here:
void dynamic_ipi_teardown(void)

> +{
> +	if (!ipi_nmi_desc)
> +		return;
> +
> +	disable_percpu_nmi(ipi_nmi_id);
> +	teardown_percpu_nmi(ipi_nmi_id);
> +}
> +
> +void __init set_smp_dynamic_ipi(int ipi)
> +{
> +	if (!request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number)) {
> +		ipi_nmi_desc = irq_to_desc(ipi);
> +		ipi_nmi_id = ipi;
> +	}
> +}
> -- 

Otherwise, looks good to me. Please feel free to add:

	Reviewed-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Thanks,
Masa

Re: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs

[Masayoshi Mizuma]

On Mon, Nov 02, 2020 at 05:14:42PM +0530, Sumit Garg wrote:
> Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a
> special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
> handler update in case of SGIs.
> 
> Also, enable NMI support prior to gic_smp_init() as allocation of SGIs
> as IRQs/NMIs happen as part of this routine.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++--------
>  1 file changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 16fecc0..7010ae2 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d)
>  static int gic_irq_nmi_setup(struct irq_data *d)
>  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
> +	u32 idx;
>  
>  	if (!gic_supports_nmi())
>  		return -EINVAL;
> @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  		return -EINVAL;
>  
>  	/* desc lock should already be held */
> -	if (gic_irq_in_rdist(d)) {
> -		u32 idx = gic_get_ppi_index(d);
> +	switch (get_intid_range(d)) {
> +	case SGI_RANGE:
> +		break;
> +	case PPI_RANGE:
> +	case EPPI_RANGE:
> +		idx = gic_get_ppi_index(d);
>  
>  		/* Setting up PPI as NMI, only switch handler for first NMI */
>  		if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
>  			refcount_set(&ppi_nmi_refs[idx], 1);
>  			desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
>  		}
> -	} else {
> +		break;
> +	default:
>  		desc->handle_irq = handle_fasteoi_nmi;
> +		break;
>  	}
>  
>  	gic_irq_set_prio(d, GICD_INT_NMI_PRI);
> @@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  static void gic_irq_nmi_teardown(struct irq_data *d)
>  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
> +	u32 idx;
>  
>  	if (WARN_ON(!gic_supports_nmi()))
>  		return;
> @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
>  		return;
>  
>  	/* desc lock should already be held */
> -	if (gic_irq_in_rdist(d)) {
> -		u32 idx = gic_get_ppi_index(d);
> +	switch (get_intid_range(d)) {
> +	case SGI_RANGE:
> +		break;
> +	case PPI_RANGE:
> +	case EPPI_RANGE:
> +		idx = gic_get_ppi_index(d);
>  
>  		/* Tearing down NMI, only switch handler for last NMI */
>  		if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
>  			desc->handle_irq = handle_percpu_devid_irq;
> -	} else {
> +		break;
> +	default:
>  		desc->handle_irq = handle_fasteoi_irq;
> +		break;
>  	}
>  
>  	gic_irq_set_prio(d, GICD_INT_DEF_PRI);
> @@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
>  
>  	gic_dist_init();
>  	gic_cpu_init();
> +	gic_enable_nmi_support();
>  	gic_smp_init();
>  	gic_cpu_pm_init();
>  
> @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base,
>  			gicv2m_init(handle, gic_data.domain);
>  	}
>  
> -	gic_enable_nmi_support();
> -
>  	return 0;
>  
>  out_free:
> -- 

Looks good to me. Please feel free to add:

	Reviewed-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Thanks!
Masa

Re: [PATCH v7 3/7] arm64: smp: Assign and setup an IPI as NMI

[Masayoshi Mizuma]

On Mon, Nov 02, 2020 at 05:14:43PM +0530, Sumit Garg wrote:
> Assign an unused IPI which can be turned as NMI using ipi_nmi framework.
> Also, invoke corresponding dynamic IPI setup/teardown APIs.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  arch/arm64/kernel/smp.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 82e75fc..2e118e2 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -43,6 +43,7 @@
>  #include <asm/daifflags.h>
>  #include <asm/kvm_mmu.h>
>  #include <asm/mmu_context.h>
> +#include <asm/nmi.h>
>  #include <asm/numa.h>
>  #include <asm/processor.h>
>  #include <asm/smp_plat.h>
> @@ -962,6 +963,8 @@ static void ipi_setup(int cpu)
>  
>  	for (i = 0; i < nr_ipi; i++)
>  		enable_percpu_irq(ipi_irq_base + i, 0);
> +
> +	dynamic_ipi_setup(cpu);
>  }
>  
>  #ifdef CONFIG_HOTPLUG_CPU
> @@ -974,6 +977,8 @@ static void ipi_teardown(int cpu)
>  
>  	for (i = 0; i < nr_ipi; i++)
>  		disable_percpu_irq(ipi_irq_base + i);
> +
> +	dynamic_ipi_teardown(cpu);
>  }
>  #endif
>  
> @@ -995,6 +1000,9 @@ void __init set_smp_ipi_range(int ipi_base, int n)
>  		irq_set_status_flags(ipi_base + i, IRQ_HIDDEN);
>  	}
>  
> +	if (n > nr_ipi)
> +		set_smp_dynamic_ipi(ipi_base + nr_ipi);
> +
>  	ipi_irq_base = ipi_base;
>  
>  	/* Setup the boot CPU immediately */
> -- 

Looks good to me. Please feel free to add:

	Reviewed-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Thanks!
Masa

Re: [PATCH v7 5/7] arm64: ipi_nmi: Add support for NMI backtrace

[Masayoshi Mizuma]

On Mon, Nov 02, 2020 at 05:14:45PM +0530, Sumit Garg wrote:
> Enable NMI backtrace support on arm64 using IPI turned as an NMI
> leveraging pseudo NMIs support. It is now possible for users to get a
> backtrace of a CPU stuck in hard-lockup using magic SYSRQ.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  arch/arm64/include/asm/irq.h |  6 ++++++
>  arch/arm64/kernel/ipi_nmi.c  | 18 ++++++++++++++++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
> index b2b0c64..ef018a8 100644
> --- a/arch/arm64/include/asm/irq.h
> +++ b/arch/arm64/include/asm/irq.h
> @@ -6,6 +6,12 @@
>  
>  #include <asm-generic/irq.h>
>  
> +#ifdef CONFIG_SMP
> +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
> +					   bool exclude_self);
> +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
> +#endif
> +
>  struct pt_regs;
>  
>  static inline int nr_legacy_irqs(void)
> diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
> index a945dcf..597dcf7 100644
> --- a/arch/arm64/kernel/ipi_nmi.c
> +++ b/arch/arm64/kernel/ipi_nmi.c
> @@ -8,6 +8,7 @@
>  
>  #include <linux/interrupt.h>
>  #include <linux/irq.h>
> +#include <linux/nmi.h>
>  #include <linux/smp.h>
>  
>  #include <asm/nmi.h>
> @@ -31,11 +32,24 @@ void arm64_send_nmi(cpumask_t *mask)
>  	__ipi_send_mask(ipi_nmi_desc, mask);
>  }
>  
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +{
> +	if (!ipi_nmi_desc)
> +		return false;
> +
> +	nmi_trigger_cpumask_backtrace(mask, exclude_self, arm64_send_nmi);
> +
> +	return true;
> +}
> +
>  static irqreturn_t ipi_nmi_handler(int irq, void *data)
>  {
> -	/* nop, NMI handlers for special features can be added here. */
> +	irqreturn_t ret = IRQ_NONE;
> +
> +	if (nmi_cpu_backtrace(get_irq_regs()))
> +		ret = IRQ_HANDLED;
>  
> -	return IRQ_NONE;
> +	return ret;
>  }
>  
>  void dynamic_ipi_setup(int cpu)
> -- 

It works well with sysrq l trigger.
Please feel free to add:

	Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Thanks!
Masa

Re: [PATCH v7 1/7] arm64: Add framework to turn IPI as NMI

[Sumit Garg]

On Mon, 2 Nov 2020 at 21:03, Masayoshi Mizuma <msys.mizuma@gmail.com> wrote:
>
> On Mon, Nov 02, 2020 at 05:14:41PM +0530, Sumit Garg wrote:
> > Introduce framework to turn an IPI as NMI using pseudo NMIs. The main
> > motivation for this feature is to have an IPI that can be leveraged to
> > invoke NMI functions on other CPUs.
> >
> > And current prospective users are NMI backtrace and KGDB CPUs round-up
> > whose support is added via future patches.
> >
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > ---
> >  arch/arm64/include/asm/nmi.h | 17 ++++++++++++
> >  arch/arm64/kernel/Makefile   |  2 +-
> >  arch/arm64/kernel/ipi_nmi.c  | 65 ++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 83 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm64/include/asm/nmi.h
> >  create mode 100644 arch/arm64/kernel/ipi_nmi.c
> >
> > diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h
> > new file mode 100644
> > index 0000000..4cd14b6
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/nmi.h
> > @@ -0,0 +1,17 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __ASM_NMI_H
> > +#define __ASM_NMI_H
> > +
> > +#ifndef __ASSEMBLER__
> > +
> > +#include <linux/cpumask.h>
> > +
> > +extern bool arm64_supports_nmi(void);
> > +extern void arm64_send_nmi(cpumask_t *mask);
> > +
> > +void set_smp_dynamic_ipi(int ipi);
> > +void dynamic_ipi_setup(int cpu);
> > +void dynamic_ipi_teardown(int cpu);
> > +
> > +#endif /* !__ASSEMBLER__ */
> > +#endif
> > diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
> > index bbaf0bc..525a1e0 100644
> > --- a/arch/arm64/kernel/Makefile
> > +++ b/arch/arm64/kernel/Makefile
> > @@ -17,7 +17,7 @@ obj-y                       := debug-monitors.o entry.o irq.o fpsimd.o              \
> >                          return_address.o cpuinfo.o cpu_errata.o              \
> >                          cpufeature.o alternative.o cacheinfo.o               \
> >                          smp.o smp_spin_table.o topology.o smccc-call.o       \
> > -                        syscall.o proton-pack.o
> > +                        syscall.o proton-pack.o ipi_nmi.o
> >
> >  targets                      += efi-entry.o
> >
> > diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
> > new file mode 100644
> > index 0000000..a945dcf
> > --- /dev/null
> > +++ b/arch/arm64/kernel/ipi_nmi.c
> > @@ -0,0 +1,65 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * NMI support for IPIs
> > + *
> > + * Copyright (C) 2020 Linaro Limited
> > + * Author: Sumit Garg <sumit.garg@linaro.org>
> > + */
> > +
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > +#include <linux/smp.h>
> > +
> > +#include <asm/nmi.h>
> > +
> > +static struct irq_desc *ipi_nmi_desc __read_mostly;
> > +static int ipi_nmi_id __read_mostly;
> > +
> > +bool arm64_supports_nmi(void)
> > +{
> > +     if (ipi_nmi_desc)
> > +             return true;
> > +
> > +     return false;
> > +}
> > +
> > +void arm64_send_nmi(cpumask_t *mask)
> > +{
> > +     if (WARN_ON_ONCE(!ipi_nmi_desc))
> > +             return;
> > +
> > +     __ipi_send_mask(ipi_nmi_desc, mask);
> > +}
> > +
> > +static irqreturn_t ipi_nmi_handler(int irq, void *data)
> > +{
> > +     /* nop, NMI handlers for special features can be added here. */
> > +
> > +     return IRQ_NONE;
> > +}
> > +
>
> > +void dynamic_ipi_setup(int cpu)
>
> cpu isn't used here, so void is better?
>
> void dynamic_ipi_setup(void)
>

Ack.

> > +{
> > +     if (!ipi_nmi_desc)
> > +             return;
> > +
> > +     if (!prepare_percpu_nmi(ipi_nmi_id))
> > +             enable_percpu_nmi(ipi_nmi_id, IRQ_TYPE_NONE);
> > +}
> > +
>
> > +void dynamic_ipi_teardown(int cpu)
>
> Same as here:
> void dynamic_ipi_teardown(void)
>

Ack.

> > +{
> > +     if (!ipi_nmi_desc)
> > +             return;
> > +
> > +     disable_percpu_nmi(ipi_nmi_id);
> > +     teardown_percpu_nmi(ipi_nmi_id);
> > +}
> > +
> > +void __init set_smp_dynamic_ipi(int ipi)
> > +{
> > +     if (!request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number)) {
> > +             ipi_nmi_desc = irq_to_desc(ipi);
> > +             ipi_nmi_id = ipi;
> > +     }
> > +}
> > --
>
> Otherwise, looks good to me. Please feel free to add:
>
>         Reviewed-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
>

Thanks.

-Sumit

> Thanks,
> Masa

RE: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs

[ito-yuichi]

Hi Sumit,

> Subject: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as
> NMIs
> 
> Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a
> special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler
> update in case of SGIs.
> 
> Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as
> IRQs/NMIs happen as part of this routine.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++--------
>  1 file changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index
> 16fecc0..7010ae2 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d)
> static int gic_irq_nmi_setup(struct irq_data *d)  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
> +	u32 idx;
> 
>  	if (!gic_supports_nmi())
>  		return -EINVAL;
> @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  		return -EINVAL;
> 
>  	/* desc lock should already be held */
> -	if (gic_irq_in_rdist(d)) {
> -		u32 idx = gic_get_ppi_index(d);
> +	switch (get_intid_range(d)) {
> +	case SGI_RANGE:
> +		break;
> +	case PPI_RANGE:
> +	case EPPI_RANGE:
> +		idx = gic_get_ppi_index(d);
> 
>  		/* Setting up PPI as NMI, only switch handler for first NMI */
>  		if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
>  			refcount_set(&ppi_nmi_refs[idx], 1);
>  			desc->handle_irq =
> handle_percpu_devid_fasteoi_nmi;
>  		}
> -	} else {
> +		break;
> +	default:
>  		desc->handle_irq = handle_fasteoi_nmi;
> +		break;
>  	}
> 
>  	gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -498,6 +505,7 @@
> static int gic_irq_nmi_setup(struct irq_data *d)  static void
> gic_irq_nmi_teardown(struct irq_data *d)  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
> +	u32 idx;
> 
>  	if (WARN_ON(!gic_supports_nmi()))
>  		return;
> @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
>  		return;
> 
>  	/* desc lock should already be held */
> -	if (gic_irq_in_rdist(d)) {
> -		u32 idx = gic_get_ppi_index(d);
> +	switch (get_intid_range(d)) {
> +	case SGI_RANGE:
> +		break;
> +	case PPI_RANGE:
> +	case EPPI_RANGE:
> +		idx = gic_get_ppi_index(d);
> 
>  		/* Tearing down NMI, only switch handler for last NMI */
>  		if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
>  			desc->handle_irq = handle_percpu_devid_irq;
> -	} else {
> +		break;
> +	default:
>  		desc->handle_irq = handle_fasteoi_irq;
> +		break;
>  	}
> 
>  	gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -1708,6 +1722,7 @@
> static int __init gic_init_bases(void __iomem *dist_base,
> 
>  	gic_dist_init();
>  	gic_cpu_init();
> +	gic_enable_nmi_support();
>  	gic_smp_init();
>  	gic_cpu_pm_init();
> 
> @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem
> *dist_base,
>  			gicv2m_init(handle, gic_data.domain);
>  	}
> 
> -	gic_enable_nmi_support();
> -
>  	return 0;
> 
>  out_free:
> --
> 2.7.4

I checked for this patch and I think that's good.
I've tested this patch with FX1000 used my other patches.
The result is as follows.

$ echo 1 > /proc/sys/kernel/panic_on_rcu_stal
$ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
   : kernel panics and crash kernel boot
   : makedumpfile saves the system state at HARDLOCKUP in vmcore.

crash utility:
 #7 [fffffe0029e4fd30] lkdtm_HARDLOCKUP at fffffe0010856eec
 #8 [fffffe0029e4fd40] direct_entry at fffffe0010856c94
 #9 [fffffe0029e4fd90] full_proxy_write at fffffe001055ced0
#10 [fffffe0029e4fdd0] vfs_write at fffffe001047436c
#11 [fffffe0029e4fe10] ksys_write at fffffe001047466c
#12 [fffffe0029e4fe60] __arm64_sys_write at fffffe0010474718
#13 [fffffe0029e4fe70] do_el0_svc at fffffe00101590cc
#14 [fffffe0029e4fea0] el0_svc at fffffe0010147a30
#15 [fffffe0029e4feb0] el0_sync_handler at fffffe001014835c
#16 [fffffe0029e4fff0] el0_sync at fffffe0010142c14

Best regards,

Yuichi Ito

Re: [PATCH v7 4/7] nmi: backtrace: Allow runtime arch specific override

[Sumit Garg]

Hello arch maintainers,

On Mon, 2 Nov 2020 at 17:16, Sumit Garg <sumit.garg@linaro.org> wrote:
>
> Add a boolean return to arch_trigger_cpumask_backtrace() to support a
> use-case where a particular architecture detects at runtime if it supports
> NMI backtrace or it would like to fallback to default implementation using
> SMP cross-calls.
>
> Currently such an architecture example is arm64 supporting pseudo NMIs
> feature which is only available on platforms which have support for GICv3
> or later version.
>
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  arch/arm/include/asm/irq.h       |  2 +-
>  arch/arm/kernel/smp.c            |  3 ++-
>  arch/mips/include/asm/irq.h      |  2 +-
>  arch/mips/kernel/process.c       |  3 ++-
>  arch/powerpc/include/asm/nmi.h   |  2 +-
>  arch/powerpc/kernel/stacktrace.c |  3 ++-
>  arch/sparc/include/asm/irq_64.h  |  2 +-
>  arch/sparc/kernel/process_64.c   |  4 +++-
>  arch/x86/include/asm/irq.h       |  2 +-
>  arch/x86/kernel/apic/hw_nmi.c    |  3 ++-
>  include/linux/nmi.h              | 12 ++++--------
>  11 files changed, 20 insertions(+), 18 deletions(-)

Do you have any comments here? It would be nice to have your ack here.

-Sumit

>
> diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
> index 46d4114..54b0180 100644
> --- a/arch/arm/include/asm/irq.h
> +++ b/arch/arm/include/asm/irq.h
> @@ -31,7 +31,7 @@ void handle_IRQ(unsigned int, struct pt_regs *);
>  void init_IRQ(void);
>
>  #ifdef CONFIG_SMP
> -extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
> +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
>                                            bool exclude_self);
>  #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
>  #endif
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 48099c6e..bb20a43 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -856,7 +856,8 @@ static void raise_nmi(cpumask_t *mask)
>         __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask);
>  }
>
> -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  {
>         nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi);
> +       return true;
>  }
> diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
> index c5d3517..34f3b42 100644
> --- a/arch/mips/include/asm/irq.h
> +++ b/arch/mips/include/asm/irq.h
> @@ -78,7 +78,7 @@ extern int cp0_fdc_irq;
>
>  extern int get_c0_fdc_int(void);
>
> -void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
> +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
>                                     bool exclude_self);
>  #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
>
> diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
> index 75ebd8d..d19e672 100644
> --- a/arch/mips/kernel/process.c
> +++ b/arch/mips/kernel/process.c
> @@ -735,9 +735,10 @@ static void raise_backtrace(cpumask_t *mask)
>         }
>  }
>
> -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  {
>         nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
> +       return true;
>  }
>
>  int mips_get_process_fp_mode(struct task_struct *task)
> diff --git a/arch/powerpc/include/asm/nmi.h b/arch/powerpc/include/asm/nmi.h
> index 84b4cfe..a5eb3e2 100644
> --- a/arch/powerpc/include/asm/nmi.h
> +++ b/arch/powerpc/include/asm/nmi.h
> @@ -9,7 +9,7 @@ static inline void arch_touch_nmi_watchdog(void) {}
>  #endif
>
>  #if defined(CONFIG_NMI_IPI) && defined(CONFIG_STACKTRACE)
> -extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
> +extern bool arch_trigger_cpumask_backtrace(const cpumask_t *mask,
>                                            bool exclude_self);
>  #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
>  #endif
> diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
> index b644065..22b112a 100644
> --- a/arch/powerpc/kernel/stacktrace.c
> +++ b/arch/powerpc/kernel/stacktrace.c
> @@ -264,8 +264,9 @@ static void raise_backtrace_ipi(cpumask_t *mask)
>         }
>  }
>
> -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  {
>         nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace_ipi);
> +       return true;
>  }
>  #endif /* defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_NMI_IPI) */
> diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
> index 4d748e9..35c01ff 100644
> --- a/arch/sparc/include/asm/irq_64.h
> +++ b/arch/sparc/include/asm/irq_64.h
> @@ -87,7 +87,7 @@ static inline unsigned long get_softint(void)
>         return retval;
>  }
>
> -void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
> +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
>                                     bool exclude_self);
>  #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
>
> diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
> index a75093b..9182001 100644
> --- a/arch/sparc/kernel/process_64.c
> +++ b/arch/sparc/kernel/process_64.c
> @@ -248,7 +248,7 @@ static void __global_reg_poll(struct global_reg_snapshot *gp)
>         }
>  }
>
> -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  {
>         struct thread_info *tp = current_thread_info();
>         struct pt_regs *regs = get_irq_regs();
> @@ -303,6 +303,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>         memset(global_cpu_snapshot, 0, sizeof(global_cpu_snapshot));
>
>         spin_unlock_irqrestore(&global_cpu_snapshot_lock, flags);
> +
> +       return true;
>  }
>
>  #ifdef CONFIG_MAGIC_SYSRQ
> diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
> index 528c8a7..b7668e0 100644
> --- a/arch/x86/include/asm/irq.h
> +++ b/arch/x86/include/asm/irq.h
> @@ -47,7 +47,7 @@ extern void init_ISA_irqs(void);
>  extern void __init init_IRQ(void);
>
>  #ifdef CONFIG_X86_LOCAL_APIC
> -void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
> +bool arch_trigger_cpumask_backtrace(const struct cpumask *mask,
>                                     bool exclude_self);
>
>  #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
> diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
> index 34a992e..e7dcd28 100644
> --- a/arch/x86/kernel/apic/hw_nmi.c
> +++ b/arch/x86/kernel/apic/hw_nmi.c
> @@ -34,10 +34,11 @@ static void nmi_raise_cpu_backtrace(cpumask_t *mask)
>         apic->send_IPI_mask(mask, NMI_VECTOR);
>  }
>
> -void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
> +bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  {
>         nmi_trigger_cpumask_backtrace(mask, exclude_self,
>                                       nmi_raise_cpu_backtrace);
> +       return true;
>  }
>
>  static int nmi_cpu_backtrace_handler(unsigned int cmd, struct pt_regs *regs)
> diff --git a/include/linux/nmi.h b/include/linux/nmi.h
> index 750c7f3..cedbfc1 100644
> --- a/include/linux/nmi.h
> +++ b/include/linux/nmi.h
> @@ -143,26 +143,22 @@ static inline void touch_nmi_watchdog(void)
>  #ifdef arch_trigger_cpumask_backtrace
>  static inline bool trigger_all_cpu_backtrace(void)
>  {
> -       arch_trigger_cpumask_backtrace(cpu_online_mask, false);
> -       return true;
> +       return arch_trigger_cpumask_backtrace(cpu_online_mask, false);
>  }
>
>  static inline bool trigger_allbutself_cpu_backtrace(void)
>  {
> -       arch_trigger_cpumask_backtrace(cpu_online_mask, true);
> -       return true;
> +       return arch_trigger_cpumask_backtrace(cpu_online_mask, true);
>  }
>
>  static inline bool trigger_cpumask_backtrace(struct cpumask *mask)
>  {
> -       arch_trigger_cpumask_backtrace(mask, false);
> -       return true;
> +       return arch_trigger_cpumask_backtrace(mask, false);
>  }
>
>  static inline bool trigger_single_cpu_backtrace(int cpu)
>  {
> -       arch_trigger_cpumask_backtrace(cpumask_of(cpu), false);
> -       return true;
> +       return arch_trigger_cpumask_backtrace(cpumask_of(cpu), false);
>  }
>
>  /* generic implementation */
> --
> 2.7.4
>

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Sumit Garg]

Hi Marc,

On Mon, 2 Nov 2020 at 17:15, Sumit Garg <sumit.garg@linaro.org> wrote:
>
> With pseudo NMIs support available its possible to configure SGIs to be
> triggered as pseudo NMIs running in NMI context. And kernel features
> such as:
> - NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
>   stuck in hard lockup using magic SYSRQ.
> - kgdb relies on NMI support to round up CPUs which are stuck in hard
>   lockup state with interrupts disabled.
>
> This patch-set adds framework to turn an IPI as NMI which can be triggered
> as a pseudo NMI which in turn invokes registered NMI handlers.
>
> After this patch-set we should be able to get a backtrace for a CPU
> stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
> testcase run on Developerbox:
>
> $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
>
> NMI backtrace:
> ==============
>
> # Issue Magic SysRq to dump backtrace
>
> [  376.894502] NMI backtrace for cpu 8
> [  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> [  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> [  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
> [  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
> [  376.894520] lr : lkdtm_do_action+0x24/0x30
> [  376.894524] sp : ffff800012cebd20
> [  376.894527] pmr_save: 00000060
> [  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
> [  376.894540] x27: 0000000000000000 x26: 0000000000000000
> [  376.894550] x25: 000000000000001a x24: ffff800012cebe40
> [  376.894560] x23: 000000000000000b x22: ffff800010fc5040
> [  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
> [  376.894579] x19: 000000000000001b x18: 0000000000000010
> [  376.894588] x17: 0000000000000000 x16: 0000000000000000
> [  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
> [  376.894613] x13: 0000000000000000 x12: 0000000000000000
> [  376.894622] x11: 0000000000000007 x10: 00000000000009c0
> [  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
> [  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
> [  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
> [  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
> [  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
> [  376.894679] Call trace:
> [  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
> [  376.894686]  direct_entry+0x124/0x1c0
> [  376.894689]  full_proxy_write+0x60/0xb0
> [  376.894693]  vfs_write+0xf0/0x230
> [  376.894696]  ksys_write+0x6c/0xf8
> [  376.894699]  __arm64_sys_write+0x1c/0x28
> [  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
> [  376.894707]  do_el0_svc+0x24/0x90
> [  376.894710]  el0_sync_handler+0x180/0x2f8
> [  376.894713]  el0_sync+0x158/0x180
>
> KGDB:
> =====
>
> # Enter kdb via Magic SysRq
>
> [6]kdb> btc
> btc: cpu status: Currently on cpu 6
> Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
> <snip>
> Stack traceback for pid 555
> 0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
> CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> Call trace:
>  dump_backtrace+0x0/0x1a0
>  show_stack+0x18/0x28
>  dump_stack+0xc0/0x11c
>  kgdb_cpu_enter+0x648/0x660
>  kgdb_nmicallback+0xa0/0xa8
>  ipi_kgdb_nmicallback+0x24/0x30
>  ipi_nmi_handler+0x48/0x60
>  handle_percpu_devid_fasteoi_ipi+0x74/0x88
>  generic_handle_irq+0x30/0x48
>  handle_domain_nmi+0x48/0x80
>  gic_handle_irq+0x18c/0x34c
>  el1_irq+0xcc/0x180
>  lkdtm_HARDLOCKUP+0x8/0x18
>  direct_entry+0x124/0x1c0
>  full_proxy_write+0x60/0xb0
>  vfs_write+0xf0/0x230
>  ksys_write+0x6c/0xf8
>  __arm64_sys_write+0x1c/0x28
>  el0_svc_common.constprop.0+0x74/0x1f0
>  do_el0_svc+0x24/0x90
>  el0_sync_handler+0x180/0x2f8
>  el0_sync+0x158/0x180
> <snip>
>
> Changes in v7:
> - Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
>   mechanism to arch specific code.
> - Addressed other misc comments from Daniel.
>
> Changes in v6:
> - Two new patches: #4 and #6 which adds runtime fallback framework for
>   sysrq backtrace and kgdb roundup features.
> - Reversed order of NMI backtrace and kgdb roundup feaure patches.
> - Addressed other misc. comments from Marc.
> - I haven't picked any tags from v5 since I think there is major rework
>   involved. Masayoshi, could you please confirm if these features still
>   work for you?
>
> Changes in v5:
> - Rebased to head of upstream master.
> - Remove redundant invocation of ipi_nmi_setup().
> - Addressed misc. comments.
>
> Changes in v4:
> - Move IPI NMI framework to a separate file.
> - Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
> - Add NMI backtrace support leveraged via magic SYSRQ.
>
> Changes in v3:
> - Rebased to Marc's latest IPIs patch-set [1].
>
> [1] https://lkml.org/lkml/2020/9/1/603
>
> Changes since RFC version [1]:
> - Switch to use generic interrupt framework to turn an IPI as NMI.
> - Dependent on Marc's patch-set [2] which turns IPIs into normal
>   interrupts.
> - Addressed misc. comments from Doug on patch #4.
> - Posted kgdb NMI printk() fixup separately which has evolved since
>   to be solved using different approach via changing kgdb interception
>   of printk() in common printk() code (see patch [3]).
>
> [1] https://lkml.org/lkml/2020/4/24/328
> [2] https://lkml.org/lkml/2020/5/19/710
> [3] https://lkml.org/lkml/2020/5/20/418
>
> Sumit Garg (7):
>   arm64: Add framework to turn IPI as NMI
>   irqchip/gic-v3: Enable support for SGIs to act as NMIs
>   arm64: smp: Assign and setup an IPI as NMI
>   nmi: backtrace: Allow runtime arch specific override
>   arm64: ipi_nmi: Add support for NMI backtrace
>   kgdb: Expose default CPUs roundup fallback mechanism
>   arm64: kgdb: Roundup cpus using IPI as NMI
>

Do you have any further feedback on this patch-set?

-Sumit

>  arch/arm/include/asm/irq.h       |  2 +-
>  arch/arm/kernel/smp.c            |  3 +-
>  arch/arm64/include/asm/irq.h     |  6 +++
>  arch/arm64/include/asm/nmi.h     | 17 ++++++++
>  arch/arm64/kernel/Makefile       |  2 +-
>  arch/arm64/kernel/ipi_nmi.c      | 84 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm64/kernel/kgdb.c         | 18 +++++++++
>  arch/arm64/kernel/smp.c          |  8 ++++
>  arch/mips/include/asm/irq.h      |  2 +-
>  arch/mips/kernel/process.c       |  3 +-
>  arch/powerpc/include/asm/nmi.h   |  2 +-
>  arch/powerpc/kernel/stacktrace.c |  3 +-
>  arch/sparc/include/asm/irq_64.h  |  2 +-
>  arch/sparc/kernel/process_64.c   |  4 +-
>  arch/x86/include/asm/irq.h       |  2 +-
>  arch/x86/kernel/apic/hw_nmi.c    |  3 +-
>  drivers/irqchip/irq-gic-v3.c     | 29 ++++++++++----
>  include/linux/kgdb.h             | 12 ++++++
>  include/linux/nmi.h              | 12 ++----
>  kernel/debug/debug_core.c        |  8 +++-
>  20 files changed, 194 insertions(+), 28 deletions(-)
>  create mode 100644 arch/arm64/include/asm/nmi.h
>  create mode 100644 arch/arm64/kernel/ipi_nmi.c
>
> --
> 2.7.4
>

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Marc Zyngier]

On 2021-01-05 10:34, Sumit Garg wrote:

> Do you have any further feedback on this patch-set?

None at the moment. We have tons of issues to solve with the arm64
interrupt entry code vs instrumentation at the moment, so it is
pretty much at the bottom of the priority list for now.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v7 7/7] arm64: kgdb: Roundup cpus using IPI as NMI

[Chen-Yu Tsai]

Hi,

On Mon, Nov 2, 2020 at 7:47 PM Sumit Garg <sumit.garg@linaro.org> wrote:
>
> arm64 platforms with GICv3 or later supports pseudo NMIs which can be
> leveraged to roundup CPUs which are stuck in hard lockup state with
> interrupts disabled that wouldn't be possible with a normal IPI.
>
> So instead switch to roundup CPUs using IPI turned as NMI. And in
> case a particular arm64 platform doesn't supports pseudo NMIs,
> it will switch back to default kgdb CPUs roundup mechanism.
>
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  arch/arm64/kernel/ipi_nmi.c |  5 +++++
>  arch/arm64/kernel/kgdb.c    | 18 ++++++++++++++++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c
> index 597dcf7..898d69c 100644
> --- a/arch/arm64/kernel/ipi_nmi.c
> +++ b/arch/arm64/kernel/ipi_nmi.c
> @@ -8,6 +8,7 @@
>
>  #include <linux/interrupt.h>
>  #include <linux/irq.h>
> +#include <linux/kgdb.h>
>  #include <linux/nmi.h>
>  #include <linux/smp.h>
>
> @@ -45,10 +46,14 @@ bool arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
>  static irqreturn_t ipi_nmi_handler(int irq, void *data)
>  {
>         irqreturn_t ret = IRQ_NONE;
> +       unsigned int cpu = smp_processor_id();
>
>         if (nmi_cpu_backtrace(get_irq_regs()))
>                 ret = IRQ_HANDLED;
>
> +       if (!kgdb_nmicallback(cpu, get_irq_regs()))

This fails to compile if CONFIG_KGDB isn't enabled.


ChenYu


> +               ret = IRQ_HANDLED;
> +
>         return ret;
>  }
>
> diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
> index 1a157ca3..371b176 100644
> --- a/arch/arm64/kernel/kgdb.c
> +++ b/arch/arm64/kernel/kgdb.c
> @@ -17,6 +17,7 @@
>
>  #include <asm/debug-monitors.h>
>  #include <asm/insn.h>
> +#include <asm/nmi.h>
>  #include <asm/traps.h>
>
>  struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
> @@ -353,3 +354,20 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
>         return aarch64_insn_write((void *)bpt->bpt_addr,
>                         *(u32 *)bpt->saved_instr);
>  }
> +
> +void kgdb_roundup_cpus(void)
> +{
> +       struct cpumask mask;
> +
> +       if (!arm64_supports_nmi()) {
> +               kgdb_smp_call_nmi_hook();
> +               return;
> +       }
> +
> +       cpumask_copy(&mask, cpu_online_mask);
> +       cpumask_clear_cpu(raw_smp_processor_id(), &mask);
> +       if (cpumask_empty(&mask))
> +               return;
> +
> +       arm64_send_nmi(&mask);
> +}
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Chen-Yu Tsai]

On Mon, Nov 2, 2020 at 7:46 PM Sumit Garg <sumit.garg@linaro.org> wrote:
>
> With pseudo NMIs support available its possible to configure SGIs to be
> triggered as pseudo NMIs running in NMI context. And kernel features
> such as:
> - NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
>   stuck in hard lockup using magic SYSRQ.
> - kgdb relies on NMI support to round up CPUs which are stuck in hard
>   lockup state with interrupts disabled.
>
> This patch-set adds framework to turn an IPI as NMI which can be triggered
> as a pseudo NMI which in turn invokes registered NMI handlers.
>
> After this patch-set we should be able to get a backtrace for a CPU
> stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
> testcase run on Developerbox:
>
> $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
>
> NMI backtrace:
> ==============
>
> # Issue Magic SysRq to dump backtrace
>
> [  376.894502] NMI backtrace for cpu 8
> [  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> [  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> [  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
> [  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
> [  376.894520] lr : lkdtm_do_action+0x24/0x30
> [  376.894524] sp : ffff800012cebd20
> [  376.894527] pmr_save: 00000060
> [  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
> [  376.894540] x27: 0000000000000000 x26: 0000000000000000
> [  376.894550] x25: 000000000000001a x24: ffff800012cebe40
> [  376.894560] x23: 000000000000000b x22: ffff800010fc5040
> [  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
> [  376.894579] x19: 000000000000001b x18: 0000000000000010
> [  376.894588] x17: 0000000000000000 x16: 0000000000000000
> [  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
> [  376.894613] x13: 0000000000000000 x12: 0000000000000000
> [  376.894622] x11: 0000000000000007 x10: 00000000000009c0
> [  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
> [  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
> [  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
> [  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
> [  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
> [  376.894679] Call trace:
> [  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
> [  376.894686]  direct_entry+0x124/0x1c0
> [  376.894689]  full_proxy_write+0x60/0xb0
> [  376.894693]  vfs_write+0xf0/0x230
> [  376.894696]  ksys_write+0x6c/0xf8
> [  376.894699]  __arm64_sys_write+0x1c/0x28
> [  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
> [  376.894707]  do_el0_svc+0x24/0x90
> [  376.894710]  el0_sync_handler+0x180/0x2f8
> [  376.894713]  el0_sync+0x158/0x180
>
> KGDB:
> =====
>
> # Enter kdb via Magic SysRq
>
> [6]kdb> btc
> btc: cpu status: Currently on cpu 6
> Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
> <snip>
> Stack traceback for pid 555
> 0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
> CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> Call trace:
>  dump_backtrace+0x0/0x1a0
>  show_stack+0x18/0x28
>  dump_stack+0xc0/0x11c
>  kgdb_cpu_enter+0x648/0x660
>  kgdb_nmicallback+0xa0/0xa8
>  ipi_kgdb_nmicallback+0x24/0x30
>  ipi_nmi_handler+0x48/0x60
>  handle_percpu_devid_fasteoi_ipi+0x74/0x88
>  generic_handle_irq+0x30/0x48
>  handle_domain_nmi+0x48/0x80
>  gic_handle_irq+0x18c/0x34c
>  el1_irq+0xcc/0x180
>  lkdtm_HARDLOCKUP+0x8/0x18
>  direct_entry+0x124/0x1c0
>  full_proxy_write+0x60/0xb0
>  vfs_write+0xf0/0x230
>  ksys_write+0x6c/0xf8
>  __arm64_sys_write+0x1c/0x28
>  el0_svc_common.constprop.0+0x74/0x1f0
>  do_el0_svc+0x24/0x90
>  el0_sync_handler+0x180/0x2f8
>  el0_sync+0x158/0x180
> <snip>
>
> Changes in v7:
> - Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
>   mechanism to arch specific code.
> - Addressed other misc comments from Daniel.
>
> Changes in v6:
> - Two new patches: #4 and #6 which adds runtime fallback framework for
>   sysrq backtrace and kgdb roundup features.
> - Reversed order of NMI backtrace and kgdb roundup feaure patches.
> - Addressed other misc. comments from Marc.
> - I haven't picked any tags from v5 since I think there is major rework
>   involved. Masayoshi, could you please confirm if these features still
>   work for you?
>
> Changes in v5:
> - Rebased to head of upstream master.
> - Remove redundant invocation of ipi_nmi_setup().
> - Addressed misc. comments.
>
> Changes in v4:
> - Move IPI NMI framework to a separate file.
> - Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
> - Add NMI backtrace support leveraged via magic SYSRQ.
>
> Changes in v3:
> - Rebased to Marc's latest IPIs patch-set [1].
>
> [1] https://lkml.org/lkml/2020/9/1/603
>
> Changes since RFC version [1]:
> - Switch to use generic interrupt framework to turn an IPI as NMI.
> - Dependent on Marc's patch-set [2] which turns IPIs into normal
>   interrupts.
> - Addressed misc. comments from Doug on patch #4.
> - Posted kgdb NMI printk() fixup separately which has evolved since
>   to be solved using different approach via changing kgdb interception
>   of printk() in common printk() code (see patch [3]).
>
> [1] https://lkml.org/lkml/2020/4/24/328
> [2] https://lkml.org/lkml/2020/5/19/710
> [3] https://lkml.org/lkml/2020/5/20/418
>
> Sumit Garg (7):
>   arm64: Add framework to turn IPI as NMI
>   irqchip/gic-v3: Enable support for SGIs to act as NMIs
>   arm64: smp: Assign and setup an IPI as NMI
>   nmi: backtrace: Allow runtime arch specific override
>   arm64: ipi_nmi: Add support for NMI backtrace
>   kgdb: Expose default CPUs roundup fallback mechanism
>   arm64: kgdb: Roundup cpus using IPI as NMI

Tested-by: Chen-Yu Tsai <wens@csie.org>

on an ROC-RK3399-PC.

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Sumit Garg]

On Fri, 25 Jun 2021 at 20:26, Chen-Yu Tsai <wens@kernel.org> wrote:
>
> On Mon, Nov 2, 2020 at 7:46 PM Sumit Garg <sumit.garg@linaro.org> wrote:
> >
> > With pseudo NMIs support available its possible to configure SGIs to be
> > triggered as pseudo NMIs running in NMI context. And kernel features
> > such as:
> > - NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
> >   stuck in hard lockup using magic SYSRQ.
> > - kgdb relies on NMI support to round up CPUs which are stuck in hard
> >   lockup state with interrupts disabled.
> >
> > This patch-set adds framework to turn an IPI as NMI which can be triggered
> > as a pseudo NMI which in turn invokes registered NMI handlers.
> >
> > After this patch-set we should be able to get a backtrace for a CPU
> > stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
> > testcase run on Developerbox:
> >
> > $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
> >
> > NMI backtrace:
> > ==============
> >
> > # Issue Magic SysRq to dump backtrace
> >
> > [  376.894502] NMI backtrace for cpu 8
> > [  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > [  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > [  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
> > [  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
> > [  376.894520] lr : lkdtm_do_action+0x24/0x30
> > [  376.894524] sp : ffff800012cebd20
> > [  376.894527] pmr_save: 00000060
> > [  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
> > [  376.894540] x27: 0000000000000000 x26: 0000000000000000
> > [  376.894550] x25: 000000000000001a x24: ffff800012cebe40
> > [  376.894560] x23: 000000000000000b x22: ffff800010fc5040
> > [  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
> > [  376.894579] x19: 000000000000001b x18: 0000000000000010
> > [  376.894588] x17: 0000000000000000 x16: 0000000000000000
> > [  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
> > [  376.894613] x13: 0000000000000000 x12: 0000000000000000
> > [  376.894622] x11: 0000000000000007 x10: 00000000000009c0
> > [  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
> > [  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
> > [  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
> > [  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
> > [  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
> > [  376.894679] Call trace:
> > [  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
> > [  376.894686]  direct_entry+0x124/0x1c0
> > [  376.894689]  full_proxy_write+0x60/0xb0
> > [  376.894693]  vfs_write+0xf0/0x230
> > [  376.894696]  ksys_write+0x6c/0xf8
> > [  376.894699]  __arm64_sys_write+0x1c/0x28
> > [  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
> > [  376.894707]  do_el0_svc+0x24/0x90
> > [  376.894710]  el0_sync_handler+0x180/0x2f8
> > [  376.894713]  el0_sync+0x158/0x180
> >
> > KGDB:
> > =====
> >
> > # Enter kdb via Magic SysRq
> >
> > [6]kdb> btc
> > btc: cpu status: Currently on cpu 6
> > Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
> > <snip>
> > Stack traceback for pid 555
> > 0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
> > CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > Call trace:
> >  dump_backtrace+0x0/0x1a0
> >  show_stack+0x18/0x28
> >  dump_stack+0xc0/0x11c
> >  kgdb_cpu_enter+0x648/0x660
> >  kgdb_nmicallback+0xa0/0xa8
> >  ipi_kgdb_nmicallback+0x24/0x30
> >  ipi_nmi_handler+0x48/0x60
> >  handle_percpu_devid_fasteoi_ipi+0x74/0x88
> >  generic_handle_irq+0x30/0x48
> >  handle_domain_nmi+0x48/0x80
> >  gic_handle_irq+0x18c/0x34c
> >  el1_irq+0xcc/0x180
> >  lkdtm_HARDLOCKUP+0x8/0x18
> >  direct_entry+0x124/0x1c0
> >  full_proxy_write+0x60/0xb0
> >  vfs_write+0xf0/0x230
> >  ksys_write+0x6c/0xf8
> >  __arm64_sys_write+0x1c/0x28
> >  el0_svc_common.constprop.0+0x74/0x1f0
> >  do_el0_svc+0x24/0x90
> >  el0_sync_handler+0x180/0x2f8
> >  el0_sync+0x158/0x180
> > <snip>
> >
> > Changes in v7:
> > - Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
> >   mechanism to arch specific code.
> > - Addressed other misc comments from Daniel.
> >
> > Changes in v6:
> > - Two new patches: #4 and #6 which adds runtime fallback framework for
> >   sysrq backtrace and kgdb roundup features.
> > - Reversed order of NMI backtrace and kgdb roundup feaure patches.
> > - Addressed other misc. comments from Marc.
> > - I haven't picked any tags from v5 since I think there is major rework
> >   involved. Masayoshi, could you please confirm if these features still
> >   work for you?
> >
> > Changes in v5:
> > - Rebased to head of upstream master.
> > - Remove redundant invocation of ipi_nmi_setup().
> > - Addressed misc. comments.
> >
> > Changes in v4:
> > - Move IPI NMI framework to a separate file.
> > - Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
> > - Add NMI backtrace support leveraged via magic SYSRQ.
> >
> > Changes in v3:
> > - Rebased to Marc's latest IPIs patch-set [1].
> >
> > [1] https://lkml.org/lkml/2020/9/1/603
> >
> > Changes since RFC version [1]:
> > - Switch to use generic interrupt framework to turn an IPI as NMI.
> > - Dependent on Marc's patch-set [2] which turns IPIs into normal
> >   interrupts.
> > - Addressed misc. comments from Doug on patch #4.
> > - Posted kgdb NMI printk() fixup separately which has evolved since
> >   to be solved using different approach via changing kgdb interception
> >   of printk() in common printk() code (see patch [3]).
> >
> > [1] https://lkml.org/lkml/2020/4/24/328
> > [2] https://lkml.org/lkml/2020/5/19/710
> > [3] https://lkml.org/lkml/2020/5/20/418
> >
> > Sumit Garg (7):
> >   arm64: Add framework to turn IPI as NMI
> >   irqchip/gic-v3: Enable support for SGIs to act as NMIs
> >   arm64: smp: Assign and setup an IPI as NMI
> >   nmi: backtrace: Allow runtime arch specific override
> >   arm64: ipi_nmi: Add support for NMI backtrace
> >   kgdb: Expose default CPUs roundup fallback mechanism
> >   arm64: kgdb: Roundup cpus using IPI as NMI
>
> Tested-by: Chen-Yu Tsai <wens@csie.org>
>
> on an ROC-RK3399-PC.

Thanks for testing this feature.

-Sumit

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Sumit Garg]

On Tue, 5 Jan 2021 at 16:13, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2021-01-05 10:34, Sumit Garg wrote:
>
> > Do you have any further feedback on this patch-set?
>
> None at the moment. We have tons of issues to solve with the arm64
> interrupt entry code vs instrumentation at the moment, so it is
> pretty much at the bottom of the priority list for now.
>

I hope you were able to resolve most of the issues. Is it an
appropriate time to have a relook at this pseudo NMI feature?

-Sumit

> Thanks,
>
>          M.
> --
> Jazz is not dead. It just smells funny...

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Masayoshi Mizuma]

On Wed, Jul 07, 2021 at 11:29:29AM +0530, Sumit Garg wrote:
> On Fri, 25 Jun 2021 at 20:26, Chen-Yu Tsai <wens@kernel.org> wrote:
> >
> > On Mon, Nov 2, 2020 at 7:46 PM Sumit Garg <sumit.garg@linaro.org> wrote:
> > >
> > > With pseudo NMIs support available its possible to configure SGIs to be
> > > triggered as pseudo NMIs running in NMI context. And kernel features
> > > such as:
> > > - NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
> > >   stuck in hard lockup using magic SYSRQ.
> > > - kgdb relies on NMI support to round up CPUs which are stuck in hard
> > >   lockup state with interrupts disabled.
> > >
> > > This patch-set adds framework to turn an IPI as NMI which can be triggered
> > > as a pseudo NMI which in turn invokes registered NMI handlers.
> > >
> > > After this patch-set we should be able to get a backtrace for a CPU
> > > stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
> > > testcase run on Developerbox:
> > >
> > > $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
> > >
> > > NMI backtrace:
> > > ==============
> > >
> > > # Issue Magic SysRq to dump backtrace
> > >
> > > [  376.894502] NMI backtrace for cpu 8
> > > [  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > > [  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > > [  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
> > > [  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
> > > [  376.894520] lr : lkdtm_do_action+0x24/0x30
> > > [  376.894524] sp : ffff800012cebd20
> > > [  376.894527] pmr_save: 00000060
> > > [  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
> > > [  376.894540] x27: 0000000000000000 x26: 0000000000000000
> > > [  376.894550] x25: 000000000000001a x24: ffff800012cebe40
> > > [  376.894560] x23: 000000000000000b x22: ffff800010fc5040
> > > [  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
> > > [  376.894579] x19: 000000000000001b x18: 0000000000000010
> > > [  376.894588] x17: 0000000000000000 x16: 0000000000000000
> > > [  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
> > > [  376.894613] x13: 0000000000000000 x12: 0000000000000000
> > > [  376.894622] x11: 0000000000000007 x10: 00000000000009c0
> > > [  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
> > > [  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
> > > [  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
> > > [  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
> > > [  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
> > > [  376.894679] Call trace:
> > > [  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
> > > [  376.894686]  direct_entry+0x124/0x1c0
> > > [  376.894689]  full_proxy_write+0x60/0xb0
> > > [  376.894693]  vfs_write+0xf0/0x230
> > > [  376.894696]  ksys_write+0x6c/0xf8
> > > [  376.894699]  __arm64_sys_write+0x1c/0x28
> > > [  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
> > > [  376.894707]  do_el0_svc+0x24/0x90
> > > [  376.894710]  el0_sync_handler+0x180/0x2f8
> > > [  376.894713]  el0_sync+0x158/0x180
> > >
> > > KGDB:
> > > =====
> > >
> > > # Enter kdb via Magic SysRq
> > >
> > > [6]kdb> btc
> > > btc: cpu status: Currently on cpu 6
> > > Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
> > > <snip>
> > > Stack traceback for pid 555
> > > 0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
> > > CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > > Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > > Call trace:
> > >  dump_backtrace+0x0/0x1a0
> > >  show_stack+0x18/0x28
> > >  dump_stack+0xc0/0x11c
> > >  kgdb_cpu_enter+0x648/0x660
> > >  kgdb_nmicallback+0xa0/0xa8
> > >  ipi_kgdb_nmicallback+0x24/0x30
> > >  ipi_nmi_handler+0x48/0x60
> > >  handle_percpu_devid_fasteoi_ipi+0x74/0x88
> > >  generic_handle_irq+0x30/0x48
> > >  handle_domain_nmi+0x48/0x80
> > >  gic_handle_irq+0x18c/0x34c
> > >  el1_irq+0xcc/0x180
> > >  lkdtm_HARDLOCKUP+0x8/0x18
> > >  direct_entry+0x124/0x1c0
> > >  full_proxy_write+0x60/0xb0
> > >  vfs_write+0xf0/0x230
> > >  ksys_write+0x6c/0xf8
> > >  __arm64_sys_write+0x1c/0x28
> > >  el0_svc_common.constprop.0+0x74/0x1f0
> > >  do_el0_svc+0x24/0x90
> > >  el0_sync_handler+0x180/0x2f8
> > >  el0_sync+0x158/0x180
> > > <snip>
> > >
> > > Changes in v7:
> > > - Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
> > >   mechanism to arch specific code.
> > > - Addressed other misc comments from Daniel.
> > >
> > > Changes in v6:
> > > - Two new patches: #4 and #6 which adds runtime fallback framework for
> > >   sysrq backtrace and kgdb roundup features.
> > > - Reversed order of NMI backtrace and kgdb roundup feaure patches.
> > > - Addressed other misc. comments from Marc.
> > > - I haven't picked any tags from v5 since I think there is major rework
> > >   involved. Masayoshi, could you please confirm if these features still
> > >   work for you?
> > >
> > > Changes in v5:
> > > - Rebased to head of upstream master.
> > > - Remove redundant invocation of ipi_nmi_setup().
> > > - Addressed misc. comments.
> > >
> > > Changes in v4:
> > > - Move IPI NMI framework to a separate file.
> > > - Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
> > > - Add NMI backtrace support leveraged via magic SYSRQ.
> > >
> > > Changes in v3:
> > > - Rebased to Marc's latest IPIs patch-set [1].
> > >
> > > [1] https://lkml.org/lkml/2020/9/1/603
> > >
> > > Changes since RFC version [1]:
> > > - Switch to use generic interrupt framework to turn an IPI as NMI.
> > > - Dependent on Marc's patch-set [2] which turns IPIs into normal
> > >   interrupts.
> > > - Addressed misc. comments from Doug on patch #4.
> > > - Posted kgdb NMI printk() fixup separately which has evolved since
> > >   to be solved using different approach via changing kgdb interception
> > >   of printk() in common printk() code (see patch [3]).
> > >
> > > [1] https://lkml.org/lkml/2020/4/24/328
> > > [2] https://lkml.org/lkml/2020/5/19/710
> > > [3] https://lkml.org/lkml/2020/5/20/418
> > >
> > > Sumit Garg (7):
> > >   arm64: Add framework to turn IPI as NMI
> > >   irqchip/gic-v3: Enable support for SGIs to act as NMIs
> > >   arm64: smp: Assign and setup an IPI as NMI
> > >   nmi: backtrace: Allow runtime arch specific override
> > >   arm64: ipi_nmi: Add support for NMI backtrace
> > >   kgdb: Expose default CPUs roundup fallback mechanism
> > >   arm64: kgdb: Roundup cpus using IPI as NMI
> >
> > Tested-by: Chen-Yu Tsai <wens@csie.org>
> >
> > on an ROC-RK3399-PC.
> 
> Thanks for testing this feature.
> 
> -Sumit

Hello Sumit,

How is this patch series going?

- Masa

Re: [PATCH v7 0/7] arm64: Add framework to turn an IPI as NMI

[Sumit Garg]

Hi Masa,

On Thu, 13 Jan 2022 at 01:01, Masayoshi Mizuma <msys.mizuma@gmail.com> wrote:
>
> On Wed, Jul 07, 2021 at 11:29:29AM +0530, Sumit Garg wrote:
> > On Fri, 25 Jun 2021 at 20:26, Chen-Yu Tsai <wens@kernel.org> wrote:
> > >
> > > On Mon, Nov 2, 2020 at 7:46 PM Sumit Garg <sumit.garg@linaro.org> wrote:
> > > >
> > > > With pseudo NMIs support available its possible to configure SGIs to be
> > > > triggered as pseudo NMIs running in NMI context. And kernel features
> > > > such as:
> > > > - NMI backtrace can leverage IPI turned as NMI to get a backtrace of CPU
> > > >   stuck in hard lockup using magic SYSRQ.
> > > > - kgdb relies on NMI support to round up CPUs which are stuck in hard
> > > >   lockup state with interrupts disabled.
> > > >
> > > > This patch-set adds framework to turn an IPI as NMI which can be triggered
> > > > as a pseudo NMI which in turn invokes registered NMI handlers.
> > > >
> > > > After this patch-set we should be able to get a backtrace for a CPU
> > > > stuck in HARDLOCKUP. Have a look at an examples below from a hard lockup
> > > > testcase run on Developerbox:
> > > >
> > > > $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
> > > >
> > > > NMI backtrace:
> > > > ==============
> > > >
> > > > # Issue Magic SysRq to dump backtrace
> > > >
> > > > [  376.894502] NMI backtrace for cpu 8
> > > > [  376.894506] CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > > > [  376.894510] Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > > > [  376.894514] pstate: 40000005 (nZcv daif -PAN -UAO BTYPE=--)
> > > > [  376.894517] pc : lkdtm_HARDLOCKUP+0x8/0x18
> > > > [  376.894520] lr : lkdtm_do_action+0x24/0x30
> > > > [  376.894524] sp : ffff800012cebd20
> > > > [  376.894527] pmr_save: 00000060
> > > > [  376.894530] x29: ffff800012cebd20 x28: ffff000875ae8000
> > > > [  376.894540] x27: 0000000000000000 x26: 0000000000000000
> > > > [  376.894550] x25: 000000000000001a x24: ffff800012cebe40
> > > > [  376.894560] x23: 000000000000000b x22: ffff800010fc5040
> > > > [  376.894569] x21: ffff000878b61000 x20: ffff8000113b2870
> > > > [  376.894579] x19: 000000000000001b x18: 0000000000000010
> > > > [  376.894588] x17: 0000000000000000 x16: 0000000000000000
> > > > [  376.894598] x15: ffff000875ae8470 x14: 00000000000002ad
> > > > [  376.894613] x13: 0000000000000000 x12: 0000000000000000
> > > > [  376.894622] x11: 0000000000000007 x10: 00000000000009c0
> > > > [  376.894631] x9 : ffff800012ceba80 x8 : ffff000875ae8a20
> > > > [  376.894641] x7 : ffff00087f6b3280 x6 : ffff00087f6b3200
> > > > [  376.894651] x5 : 0000000000000000 x4 : ffff00087f6a91f8
> > > > [  376.894660] x3 : ffff00087f6b0120 x2 : 1aa310cec69eb500
> > > > [  376.894670] x1 : 0000000000000000 x0 : 0000000000000060
> > > > [  376.894679] Call trace:
> > > > [  376.894683]  lkdtm_HARDLOCKUP+0x8/0x18
> > > > [  376.894686]  direct_entry+0x124/0x1c0
> > > > [  376.894689]  full_proxy_write+0x60/0xb0
> > > > [  376.894693]  vfs_write+0xf0/0x230
> > > > [  376.894696]  ksys_write+0x6c/0xf8
> > > > [  376.894699]  __arm64_sys_write+0x1c/0x28
> > > > [  376.894703]  el0_svc_common.constprop.0+0x74/0x1f0
> > > > [  376.894707]  do_el0_svc+0x24/0x90
> > > > [  376.894710]  el0_sync_handler+0x180/0x2f8
> > > > [  376.894713]  el0_sync+0x158/0x180
> > > >
> > > > KGDB:
> > > > =====
> > > >
> > > > # Enter kdb via Magic SysRq
> > > >
> > > > [6]kdb> btc
> > > > btc: cpu status: Currently on cpu 6
> > > > Available cpus: 0-5(I), 6, 7(I), 8, 9-23(I)
> > > > <snip>
> > > > Stack traceback for pid 555
> > > > 0xffff000875ae8000      555      554  1    8   R  0xffff000875ae89c0  bash
> > > > CPU: 8 PID: 555 Comm: bash Not tainted 5.9.0-rc3-00740-g06ff047-dirty #242
> > > > Hardware name: Socionext SynQuacer E-series DeveloperBox, BIOS build #73 Apr  6 2020
> > > > Call trace:
> > > >  dump_backtrace+0x0/0x1a0
> > > >  show_stack+0x18/0x28
> > > >  dump_stack+0xc0/0x11c
> > > >  kgdb_cpu_enter+0x648/0x660
> > > >  kgdb_nmicallback+0xa0/0xa8
> > > >  ipi_kgdb_nmicallback+0x24/0x30
> > > >  ipi_nmi_handler+0x48/0x60
> > > >  handle_percpu_devid_fasteoi_ipi+0x74/0x88
> > > >  generic_handle_irq+0x30/0x48
> > > >  handle_domain_nmi+0x48/0x80
> > > >  gic_handle_irq+0x18c/0x34c
> > > >  el1_irq+0xcc/0x180
> > > >  lkdtm_HARDLOCKUP+0x8/0x18
> > > >  direct_entry+0x124/0x1c0
> > > >  full_proxy_write+0x60/0xb0
> > > >  vfs_write+0xf0/0x230
> > > >  ksys_write+0x6c/0xf8
> > > >  __arm64_sys_write+0x1c/0x28
> > > >  el0_svc_common.constprop.0+0x74/0x1f0
> > > >  do_el0_svc+0x24/0x90
> > > >  el0_sync_handler+0x180/0x2f8
> > > >  el0_sync+0x158/0x180
> > > > <snip>
> > > >
> > > > Changes in v7:
> > > > - Add a new library function: kgdb_smp_call_nmi_hook() to expose fallback
> > > >   mechanism to arch specific code.
> > > > - Addressed other misc comments from Daniel.
> > > >
> > > > Changes in v6:
> > > > - Two new patches: #4 and #6 which adds runtime fallback framework for
> > > >   sysrq backtrace and kgdb roundup features.
> > > > - Reversed order of NMI backtrace and kgdb roundup feaure patches.
> > > > - Addressed other misc. comments from Marc.
> > > > - I haven't picked any tags from v5 since I think there is major rework
> > > >   involved. Masayoshi, could you please confirm if these features still
> > > >   work for you?
> > > >
> > > > Changes in v5:
> > > > - Rebased to head of upstream master.
> > > > - Remove redundant invocation of ipi_nmi_setup().
> > > > - Addressed misc. comments.
> > > >
> > > > Changes in v4:
> > > > - Move IPI NMI framework to a separate file.
> > > > - Get rid of hard-coded IPI_CALL_NMI_FUNC allocation.
> > > > - Add NMI backtrace support leveraged via magic SYSRQ.
> > > >
> > > > Changes in v3:
> > > > - Rebased to Marc's latest IPIs patch-set [1].
> > > >
> > > > [1] https://lkml.org/lkml/2020/9/1/603
> > > >
> > > > Changes since RFC version [1]:
> > > > - Switch to use generic interrupt framework to turn an IPI as NMI.
> > > > - Dependent on Marc's patch-set [2] which turns IPIs into normal
> > > >   interrupts.
> > > > - Addressed misc. comments from Doug on patch #4.
> > > > - Posted kgdb NMI printk() fixup separately which has evolved since
> > > >   to be solved using different approach via changing kgdb interception
> > > >   of printk() in common printk() code (see patch [3]).
> > > >
> > > > [1] https://lkml.org/lkml/2020/4/24/328
> > > > [2] https://lkml.org/lkml/2020/5/19/710
> > > > [3] https://lkml.org/lkml/2020/5/20/418
> > > >
> > > > Sumit Garg (7):
> > > >   arm64: Add framework to turn IPI as NMI
> > > >   irqchip/gic-v3: Enable support for SGIs to act as NMIs
> > > >   arm64: smp: Assign and setup an IPI as NMI
> > > >   nmi: backtrace: Allow runtime arch specific override
> > > >   arm64: ipi_nmi: Add support for NMI backtrace
> > > >   kgdb: Expose default CPUs roundup fallback mechanism
> > > >   arm64: kgdb: Roundup cpus using IPI as NMI
> > >
> > > Tested-by: Chen-Yu Tsai <wens@csie.org>
> > >
> > > on an ROC-RK3399-PC.
> >
> > Thanks for testing this feature.
> >
> > -Sumit
>
> Hello Sumit,
>
> How is this patch series going?

I am still awaiting feedback from arm64 maintainers.

arm64 maintainers,

Do you believe that features leveraging pseudo NMIs on arm64 can make
it to the mainline? Or the pseudo NMIs feature itself isn't mature
enough that we don't want to have any further users at this point?

-Sumit

>
> - Masa