From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Remi Pommarel <repk@triplefau.lt>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Yue Wang <yue.wang@amlogic.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-pci@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] clk: meson: axg: add pcie pll cml gating
Date: Sun, 8 Dec 2019 23:07:57 +0100 [thread overview]
Message-ID: <CAFBinCA7Tnc2M=4jxYYS_RuoLnGNprUOFDrZG_G6fhQCyb3Cig@mail.gmail.com> (raw)
In-Reply-To: <20191208210320.15539-2-repk@triplefau.lt>
Hi Remi,
On Sun, Dec 8, 2019 at 9:56 PM Remi Pommarel <repk@triplefau.lt> wrote:
[...]
> +static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26);
we already have CLKID_PCIE_CML_EN0
do you know how this new one is related (in terms of clock hierarchy)
to the existing one?
[...]
> --- a/include/dt-bindings/clock/axg-clkc.h
> +++ b/include/dt-bindings/clock/axg-clkc.h
> @@ -72,5 +72,6 @@
> #define CLKID_PCIE_CML_EN1 80
> #define CLKID_MIPI_ENABLE 81
> #define CLKID_GEN_CLK 84
> +#define CLKID_PCIE_PLL_CML_ENABLE 91
this has to be a separate patch if you want the .dts patch to go into
the same cycle
the .dts change depends on this one. what we typically do is to apply
the dt-bindings patches to a separate clock branch, create an
immutable tag and then Kevin pulls that into his dt64 branch.
the clock controller changes go into a separate patch in the
clk-meson/drivers branch to avoid conflicts with other driver changes
Martin
next prev parent reply other threads:[~2019-12-08 22:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-08 21:03 [PATCH 0/2] PCI: amlogic: Make PCIe working reliably on AXG platforms Remi Pommarel
2019-12-08 21:03 ` [PATCH 1/2] clk: meson: axg: add pcie pll cml gating Remi Pommarel
2019-12-08 22:07 ` Martin Blumenstingl [this message]
2019-12-08 21:03 ` [PATCH 2/2] PCI: amlogic: Use PCIe pll gate when available Remi Pommarel
2019-12-09 11:03 ` Andrew Murray
2019-12-15 11:38 ` Remi Pommarel
2019-12-09 8:32 ` [PATCH 0/2] PCI: amlogic: Make PCIe working reliably on AXG platforms Jerome Brunet
2019-12-15 11:36 ` Remi Pommarel
2019-12-15 20:44 ` Martin Blumenstingl
2019-12-16 8:47 ` Jerome Brunet
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