[PATCH v2 0/2] clk: meson: g12a: Add CPU Clock support

[PATCH v2 0/2] clk: meson: g12a: Add CPU Clock support

[Neil Armstrong]

This patchset adds support for the clock tree feeding the 4xCortex A53
cpu cluster.

This patchet does not handle clock changing, this will be added in a
secondary patchset.

The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
muxes.

The CPU clock must be switched to a safe clock while changing the clocks
before the non-glitch muxes. Proper support will be added later.

In this patchset, clocks are set read-only.

Changes since v1:
- moved to clk_regmap_gate_ro_ops for R/O gates
- added comments with datasheet field names
- moved pribate bindings changes to driver patch
- removed invalid PCIE IDs

Neil Armstrong (2):
  clk: meson-g12a: add cpu clock bindings
  clk: meson: g12a: add cpu clocks

 drivers/clk/meson/g12a.c              | 350 ++++++++++++++++++++++++++
 drivers/clk/meson/g12a.h              |  22 +-
 include/dt-bindings/clock/g12a-clkc.h |   1 +
 3 files changed, 372 insertions(+), 1 deletion(-)

-- 
2.20.1

[PATCH v2 1/2] clk: meson-g12a: add cpu clock bindings

[Neil Armstrong]

Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since
it should be the only ID used.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 include/dt-bindings/clock/g12a-clkc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 83b657038d1e..d7bf0830c87d 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -131,5 +131,6 @@
 #define CLKID_MALI_1				174
 #define CLKID_MALI				175
 #define CLKID_MPLL_5OM				177
+#define CLKID_CPU_CLK				187
 
 #endif /* __G12A_CLKC_H */
-- 
2.20.1

[PATCH v2 2/2] clk: meson: g12a: add cpu clocks

[Neil Armstrong]

Add the Amlogic G12A Family CPU Clock tree in read/only for now.

The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
muxes.

Proper DVFS support will come in a second time.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/g12a.c | 350 +++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/g12a.h |  22 ++-
 2 files changed, 371 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 0e1ce8c03259..80a7172df2a6 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
 	},
 };
 
+static struct clk_regmap g12a_sys_pll_div16_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "sys_pll_div16_en",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "sys_pll" },
+		.num_parents = 1,
+		/*
+		 * This clock is used to debug the sys_pll range
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
+static struct clk_fixed_factor g12a_sys_pll_div16 = {
+	.mult = 1,
+	.div = 16,
+	.hw.init = &(struct clk_init_data){
+		.name = "sys_pll_div16",
+		.ops = &clk_fixed_factor_ops,
+		.parent_names = (const char *[]){ "sys_pll_div16_en" },
+		.num_parents = 1,
+	},
+};
+
+/* Datasheet names this field as "premux0" */
+static struct clk_regmap g12a_cpu_clk_dyn0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x3,
+		.shift = 0,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn0_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ IN_PREFIX "xtal",
+						  "fclk_div2",
+						  "fclk_div3" },
+		.num_parents = 3,
+	},
+};
+
+/* Datasheet names this field as "mux0_divn_tcnt" */
+static struct clk_regmap g12a_cpu_clk_dyn0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.shift = 4,
+		.width = 6,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn0_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
+		.num_parents = 1,
+	},
+};
+
+/* Datasheet names this field as "postmux0" */
+static struct clk_regmap g12a_cpu_clk_dyn0 = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x1,
+		.shift = 2,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn0",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
+						  "cpu_clk_dyn0_div" },
+		.num_parents = 2,
+	},
+};
+
+/* Datasheet names this field as "premux1" */
+static struct clk_regmap g12a_cpu_clk_dyn1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x3,
+		.shift = 16,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn1_sel",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ IN_PREFIX "xtal",
+						  "fclk_div2",
+						  "fclk_div3" },
+		.num_parents = 3,
+	},
+};
+
+/* Datasheet names this field as "Mux1_divn_tcnt" */
+static struct clk_regmap g12a_cpu_clk_dyn1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.shift = 20,
+		.width = 6,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn1_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
+		.num_parents = 1,
+	},
+};
+
+/* Datasheet names this field as "postmux1" */
+static struct clk_regmap g12a_cpu_clk_dyn1 = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x1,
+		.shift = 18,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn1",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
+						  "cpu_clk_dyn1_div" },
+		.num_parents = 2,
+	},
+};
+
+/* Datasheet names this field as "Final_dyn_mux_sel" */
+static struct clk_regmap g12a_cpu_clk_dyn = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x1,
+		.shift = 10,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_dyn",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn0",
+						  "cpu_clk_dyn1" },
+		.num_parents = 2,
+	},
+};
+
+/* Datasheet names this field as "Final_mux_sel" */
+static struct clk_regmap g12a_cpu_clk = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL0,
+		.mask = 0x1,
+		.shift = 11,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_dyn",
+						  "sys_pll" },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_div16_en = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cpu_clk_div16_en",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk" },
+		.num_parents = 1,
+		/*
+		 * This clock is used to debug the cpu_clk range
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
+static struct clk_fixed_factor g12a_cpu_clk_div16 = {
+	.mult = 1,
+	.div = 16,
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_div16",
+		.ops = &clk_fixed_factor_ops,
+		.parent_names = (const char *[]){ "cpu_clk_div16_en" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_apb_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.shift = 3,
+		.width = 3,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_apb_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_apb = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 1,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cpu_clk_apb",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_apb_div" },
+		.num_parents = 1,
+		/*
+		 * This clock is set by the ROM monitor code,
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_atb_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.shift = 6,
+		.width = 3,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_atb_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_atb = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 17,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cpu_clk_atb",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_atb_div" },
+		.num_parents = 1,
+		/*
+		 * This clock is set by the ROM monitor code,
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_axi_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.shift = 9,
+		.width = 3,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_axi_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_axi = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 18,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cpu_clk_axi",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_axi_div" },
+		.num_parents = 1,
+		/*
+		 * This clock is set by the ROM monitor code,
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_trace_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.shift = 20,
+		.width = 3,
+		.flags = CLK_DIVIDER_POWER_OF_TWO,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "cpu_clk_trace_div",
+		.ops = &clk_regmap_divider_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk" },
+		.num_parents = 1,
+	},
+};
+
+static struct clk_regmap g12a_cpu_clk_trace = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_SYS_CPU_CLK_CNTL1,
+		.bit_idx = 23,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "cpu_clk_trace",
+		.ops = &clk_regmap_gate_ro_ops,
+		.parent_names = (const char *[]){ "cpu_clk_trace_div" },
+		.num_parents = 1,
+		/*
+		 * This clock is set by the ROM monitor code,
+		 * Linux should not change it at runtime
+		 */
+	},
+};
+
 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
 	.min = 55,
 	.max = 255,
@@ -2167,6 +2479,26 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
 		[CLKID_MALI]			= &g12a_mali.hw,
 		[CLKID_MPLL_5OM_DIV]		= &g12a_mpll_50m_div.hw,
 		[CLKID_MPLL_5OM]		= &g12a_mpll_50m.hw,
+		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
+		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
+		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_dyn0_sel.hw,
+		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_dyn0_div.hw,
+		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_dyn0.hw,
+		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_dyn1_sel.hw,
+		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_dyn1_div.hw,
+		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_dyn1.hw,
+		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
+		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
+		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
+		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
+		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
+		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
+		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
+		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
+		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
+		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
+		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
+		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
 		[NR_CLKS]			= NULL,
 	},
 	.num = NR_CLKS,
@@ -2335,6 +2667,24 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&g12a_mali_1,
 	&g12a_mali,
 	&g12a_mpll_50m,
+	&g12a_sys_pll_div16_en,
+	&g12a_cpu_clk_dyn0_sel,
+	&g12a_cpu_clk_dyn0_div,
+	&g12a_cpu_clk_dyn0,
+	&g12a_cpu_clk_dyn1_sel,
+	&g12a_cpu_clk_dyn1_div,
+	&g12a_cpu_clk_dyn1,
+	&g12a_cpu_clk_dyn,
+	&g12a_cpu_clk,
+	&g12a_cpu_clk_div16_en,
+	&g12a_cpu_clk_apb_div,
+	&g12a_cpu_clk_apb,
+	&g12a_cpu_clk_atb_div,
+	&g12a_cpu_clk_atb,
+	&g12a_cpu_clk_axi_div,
+	&g12a_cpu_clk_axi,
+	&g12a_cpu_clk_trace_div,
+	&g12a_cpu_clk_trace,
 };
 
 static const struct meson_eeclkc_data g12a_clkc_data = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index f399dfe1401c..70aa469ca1cf 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -50,6 +50,7 @@
 #define HHI_GCLK_MPEG2			0x148
 #define HHI_GCLK_OTHER			0x150
 #define HHI_GCLK_OTHER2			0x154
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c
 #define HHI_VID_CLK_DIV			0x164
 #define HHI_MPEG_CLK_CNTL		0x174
 #define HHI_AUD_CLK_CNTL		0x178
@@ -166,8 +167,27 @@
 #define CLKID_MALI_0_DIV			170
 #define CLKID_MALI_1_DIV			173
 #define CLKID_MPLL_5OM_DIV			176
+#define CLKID_SYS_PLL_DIV16_EN			178
+#define CLKID_SYS_PLL_DIV16			179
+#define CLKID_CPU_CLK_DYN0_SEL			180
+#define CLKID_CPU_CLK_DYN0_DIV			181
+#define CLKID_CPU_CLK_DYN0			182
+#define CLKID_CPU_CLK_DYN1_SEL			183
+#define CLKID_CPU_CLK_DYN1_DIV			184
+#define CLKID_CPU_CLK_DYN1			185
+#define CLKID_CPU_CLK_DYN			186
+#define CLKID_CPU_CLK_DIV16_EN			188
+#define CLKID_CPU_CLK_DIV16			189
+#define CLKID_CPU_CLK_APB_DIV			190
+#define CLKID_CPU_CLK_APB			191
+#define CLKID_CPU_CLK_ATB_DIV			192
+#define CLKID_CPU_CLK_ATB			193
+#define CLKID_CPU_CLK_AXI_DIV			194
+#define CLKID_CPU_CLK_AXI			195
+#define CLKID_CPU_CLK_TRACE_DIV			196
+#define CLKID_CPU_CLK_TRACE			197
 
-#define NR_CLKS					178
+#define NR_CLKS					198
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/g12a-clkc.h>
-- 
2.20.1

Re: [PATCH v2 1/2] clk: meson-g12a: add cpu clock bindings

[Martin Blumenstingl]

On Mon, Mar 4, 2019 at 2:11 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since
> it should be the only ID used.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Re: [PATCH v2 2/2] clk: meson: g12a: add cpu clocks

[Martin Blumenstingl]

On Mon, Mar 4, 2019 at 2:12 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Add the Amlogic G12A Family CPU Clock tree in read/only for now.
>
> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
> muxes.
>
> Proper DVFS support will come in a second time.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

in my previous review I criticized that the post-dividers are not
mentioned in the description.
it's not part of v2 but after having a closer look again I think it's
not a big issue:
these CPU post-dividers are all marked as read-only and have a comment
that "ROM monitor code" manages them.

disclaimer for my "reviewed-by":
- I don't have access to the datasheet so I can't verify if the clock
tree from this patch is correct
- the latest buildroot code with G12A support
(buildroot_openlinux_kernel_4.9_fbdev_20180706) doesn't have proper
names for all clocks
- this review is based on my experience with Meson8* (where Linux also
manages the CPU clock, unlike on the GX SoCs where it's managed in
firmware)


Regards
Martin

Re: [PATCH v2 2/2] clk: meson: g12a: add cpu clocks

[Neil Armstrong]

Hi Martin,

On 05/03/2019 22:10, Martin Blumenstingl wrote:
> On Mon, Mar 4, 2019 at 2:12 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Add the Amlogic G12A Family CPU Clock tree in read/only for now.
>>
>> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
>> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
>> muxes.
>>
>> Proper DVFS support will come in a second time.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> in my previous review I criticized that the post-dividers are not
> mentioned in the description.
> it's not part of v2 but after having a closer look again I think it's
> not a big issue:
> these CPU post-dividers are all marked as read-only and have a comment
> that "ROM monitor code" manages them.

Sorry indeed I forgot to say a word about this, but you pointed the right
thing, they are only here to be complete, not to be used (for now).

Neil

> 
> disclaimer for my "reviewed-by":
> - I don't have access to the datasheet so I can't verify if the clock
> tree from this patch is correct
> - the latest buildroot code with G12A support
> (buildroot_openlinux_kernel_4.9_fbdev_20180706) doesn't have proper
> names for all clocks
> - this review is based on my experience with Meson8* (where Linux also
> manages the CPU clock, unlike on the GX SoCs where it's managed in
> firmware)
> 
> 
> Regards
> Martin
> 

Re: [PATCH v2 1/2] clk: meson-g12a: add cpu clock bindings

[Rob Herring]

On Mon,  4 Mar 2019 14:11:28 +0100, Neil Armstrong wrote:
> Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since
> it should be the only ID used.
> 
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
>  include/dt-bindings/clock/g12a-clkc.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 2/2] clk: meson: g12a: add cpu clocks

[Jerome Brunet]

On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
> Add the Amlogic G12A Family CPU Clock tree in read/only for now.
> 
> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
> muxes.
> 
> Proper DVFS support will come in a second time.
> 
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
>  drivers/clk/meson/g12a.c | 350 +++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/g12a.h |  22 ++-
>  2 files changed, 371 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 0e1ce8c03259..80a7172df2a6 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
>  	},
>  };
>  
> +static struct clk_regmap g12a_sys_pll_div16_en = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 24,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "sys_pll_div16_en",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "sys_pll" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is used to debug the sys_pll range
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
> +static struct clk_fixed_factor g12a_sys_pll_div16 = {
> +	.mult = 1,
> +	.div = 16,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "sys_pll_div16",
> +		.ops = &clk_fixed_factor_ops,
> +		.parent_names = (const char *[]){ "sys_pll_div16_en" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +/* Datasheet names this field as "premux0" */
> +static struct clk_regmap g12a_cpu_clk_dyn0_sel = {

called premux0 so g12a_cpu_clk_premux0 ?

> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x3,
> +		.shift = 0,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn0_sel",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ IN_PREFIX "xtal",
> +						  "fclk_div2",
> +						  "fclk_div3" },
> +		.num_parents = 3,
> +	},
> +};
> +
> +/* Datasheet names this field as "mux0_divn_tcnt" */
> +static struct clk_regmap g12a_cpu_clk_dyn0_div = {

g12a_cpu_clk_mux0_div ?

> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.shift = 4,
> +		.width = 6,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn0_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +/* Datasheet names this field as "postmux0" */
> +static struct clk_regmap g12a_cpu_clk_dyn0 = {

g12a_cpu_clk_postmux0 ?

> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x1,
> +		.shift = 2,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn0",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
> +						  "cpu_clk_dyn0_div" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +/* Datasheet names this field as "premux1" */
> +static struct clk_regmap g12a_cpu_clk_dyn1_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x3,
> +		.shift = 16,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn1_sel",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ IN_PREFIX "xtal",
> +						  "fclk_div2",
> +						  "fclk_div3" },
> +		.num_parents = 3,
> +	},
> +};
> +
> +/* Datasheet names this field as "Mux1_divn_tcnt" */
> +static struct clk_regmap g12a_cpu_clk_dyn1_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.shift = 20,
> +		.width = 6,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn1_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +/* Datasheet names this field as "postmux1" */
> +static struct clk_regmap g12a_cpu_clk_dyn1 = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x1,
> +		.shift = 18,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn1",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
> +						  "cpu_clk_dyn1_div" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +/* Datasheet names this field as "Final_dyn_mux_sel" */
> +static struct clk_regmap g12a_cpu_clk_dyn = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x1,
> +		.shift = 10,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_dyn",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn0",
> +						  "cpu_clk_dyn1" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +/* Datasheet names this field as "Final_mux_sel" */
> +static struct clk_regmap g12a_cpu_clk = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL0,
> +		.mask = 0x1,
> +		.shift = 11,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_dyn",
> +						  "sys_pll" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_div16_en = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 1,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "cpu_clk_div16_en",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is used to debug the cpu_clk range
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
> +static struct clk_fixed_factor g12a_cpu_clk_div16 = {
> +	.mult = 1,
> +	.div = 16,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_div16",
> +		.ops = &clk_fixed_factor_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_div16_en" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_apb_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.shift = 3,
> +		.width = 3,
> +		.flags = CLK_DIVIDER_POWER_OF_TWO,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_apb_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_apb = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 1,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "cpu_clk_apb",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_apb_div" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is set by the ROM monitor code,
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_atb_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.shift = 6,
> +		.width = 3,
> +		.flags = CLK_DIVIDER_POWER_OF_TWO,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_atb_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_atb = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 17,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "cpu_clk_atb",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_atb_div" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is set by the ROM monitor code,
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_axi_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.shift = 9,
> +		.width = 3,
> +		.flags = CLK_DIVIDER_POWER_OF_TWO,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_axi_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_axi = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 18,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "cpu_clk_axi",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_axi_div" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is set by the ROM monitor code,
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_trace_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.shift = 20,
> +		.width = 3,
> +		.flags = CLK_DIVIDER_POWER_OF_TWO,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "cpu_clk_trace_div",
> +		.ops = &clk_regmap_divider_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk" },
> +		.num_parents = 1,
> +	},
> +};
> +
> +static struct clk_regmap g12a_cpu_clk_trace = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_SYS_CPU_CLK_CNTL1,
> +		.bit_idx = 23,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "cpu_clk_trace",
> +		.ops = &clk_regmap_gate_ro_ops,
> +		.parent_names = (const char *[]){ "cpu_clk_trace_div" },
> +		.num_parents = 1,
> +		/*
> +		 * This clock is set by the ROM monitor code,
> +		 * Linux should not change it at runtime
> +		 */
> +	},
> +};
> +
>  static const struct pll_mult_range g12a_gp0_pll_mult_range = {
>  	.min = 55,
>  	.max = 255,
> @@ -2167,6 +2479,26 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>  		[CLKID_MALI]			= &g12a_mali.hw,
>  		[CLKID_MPLL_5OM_DIV]		= &g12a_mpll_50m_div.hw,
>  		[CLKID_MPLL_5OM]		= &g12a_mpll_50m.hw,
> +		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> +		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
> +		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_dyn0_sel.hw,
> +		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_dyn0_div.hw,
> +		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_dyn0.hw,
> +		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_dyn1_sel.hw,
> +		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_dyn1_div.hw,
> +		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_dyn1.hw,
> +		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
> +		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
> +		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> +		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
> +		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
> +		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
> +		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
> +		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
> +		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
> +		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
> +		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> +		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>  		[NR_CLKS]			= NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -2335,6 +2667,24 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
>  	&g12a_mali_1,
>  	&g12a_mali,
>  	&g12a_mpll_50m,
> +	&g12a_sys_pll_div16_en,
> +	&g12a_cpu_clk_dyn0_sel,
> +	&g12a_cpu_clk_dyn0_div,
> +	&g12a_cpu_clk_dyn0,
> +	&g12a_cpu_clk_dyn1_sel,
> +	&g12a_cpu_clk_dyn1_div,
> +	&g12a_cpu_clk_dyn1,
> +	&g12a_cpu_clk_dyn,
> +	&g12a_cpu_clk,
> +	&g12a_cpu_clk_div16_en,
> +	&g12a_cpu_clk_apb_div,
> +	&g12a_cpu_clk_apb,
> +	&g12a_cpu_clk_atb_div,
> +	&g12a_cpu_clk_atb,
> +	&g12a_cpu_clk_axi_div,
> +	&g12a_cpu_clk_axi,
> +	&g12a_cpu_clk_trace_div,
> +	&g12a_cpu_clk_trace,
>  };
>  
>  static const struct meson_eeclkc_data g12a_clkc_data = {
> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
> index f399dfe1401c..70aa469ca1cf 100644
> --- a/drivers/clk/meson/g12a.h
> +++ b/drivers/clk/meson/g12a.h
> @@ -50,6 +50,7 @@
>  #define HHI_GCLK_MPEG2			0x148
>  #define HHI_GCLK_OTHER			0x150
>  #define HHI_GCLK_OTHER2			0x154
> +#define HHI_SYS_CPU_CLK_CNTL1		0x15c
>  #define HHI_VID_CLK_DIV			0x164
>  #define HHI_MPEG_CLK_CNTL		0x174
>  #define HHI_AUD_CLK_CNTL		0x178
> @@ -166,8 +167,27 @@
>  #define CLKID_MALI_0_DIV			170
>  #define CLKID_MALI_1_DIV			173
>  #define CLKID_MPLL_5OM_DIV			176
> +#define CLKID_SYS_PLL_DIV16_EN			178
> +#define CLKID_SYS_PLL_DIV16			179
> +#define CLKID_CPU_CLK_DYN0_SEL			180
> +#define CLKID_CPU_CLK_DYN0_DIV			181
> +#define CLKID_CPU_CLK_DYN0			182
> +#define CLKID_CPU_CLK_DYN1_SEL			183
> +#define CLKID_CPU_CLK_DYN1_DIV			184
> +#define CLKID_CPU_CLK_DYN1			185
> +#define CLKID_CPU_CLK_DYN			186
> +#define CLKID_CPU_CLK_DIV16_EN			188
> +#define CLKID_CPU_CLK_DIV16			189
> +#define CLKID_CPU_CLK_APB_DIV			190
> +#define CLKID_CPU_CLK_APB			191
> +#define CLKID_CPU_CLK_ATB_DIV			192
> +#define CLKID_CPU_CLK_ATB			193
> +#define CLKID_CPU_CLK_AXI_DIV			194
> +#define CLKID_CPU_CLK_AXI			195
> +#define CLKID_CPU_CLK_TRACE_DIV			196
> +#define CLKID_CPU_CLK_TRACE			197
>  
> -#define NR_CLKS					178
> +#define NR_CLKS					198
>  
>  /* include the CLKIDs that have been made part of the DT binding */
>  #include <dt-bindings/clock/g12a-clkc.h>

Re: [PATCH v2 0/2] clk: meson: g12a: Add CPU Clock support

[Jerome Brunet]

On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
> This patchset adds support for the clock tree feeding the 4xCortex A53
> cpu cluster.
> 
> This patchet does not handle clock changing, this will be added in a
> secondary patchset.
> 
> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
> muxes.
> 
> The CPU clock must be switched to a safe clock while changing the clocks
> before the non-glitch muxes. Proper support will be added later.
> 
> In this patchset, clocks are set read-only.
> 
> Changes since v1:
> - moved to clk_regmap_gate_ro_ops for R/O gates
> - added comments with datasheet field names
> - moved pribate bindings changes to driver patch
> - removed invalid PCIE IDs
> 
> Neil Armstrong (2):
>   clk: meson-g12a: add cpu clock bindings
>   clk: meson: g12a: add cpu clocks
> 
>  drivers/clk/meson/g12a.c              | 350 ++++++++++++++++++++++++++
>  drivers/clk/meson/g12a.h              |  22 +-
>  include/dt-bindings/clock/g12a-clkc.h |   1 +
>  3 files changed, 372 insertions(+), 1 deletion(-)
> 

With the small naming comment on patch 2

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Re: [PATCH v2 0/2] clk: meson: g12a: Add CPU Clock support

[Neil Armstrong]

On 19/03/2019 10:39, Jerome Brunet wrote:
> On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
>> This patchset adds support for the clock tree feeding the 4xCortex A53
>> cpu cluster.
>>
>> This patchet does not handle clock changing, this will be added in a
>> secondary patchset.
>>
>> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
>> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
>> muxes.
>>
>> The CPU clock must be switched to a safe clock while changing the clocks
>> before the non-glitch muxes. Proper support will be added later.
>>
>> In this patchset, clocks are set read-only.
>>
>> Changes since v1:
>> - moved to clk_regmap_gate_ro_ops for R/O gates
>> - added comments with datasheet field names
>> - moved pribate bindings changes to driver patch
>> - removed invalid PCIE IDs
>>
>> Neil Armstrong (2):
>>   clk: meson-g12a: add cpu clock bindings
>>   clk: meson: g12a: add cpu clocks
>>
>>  drivers/clk/meson/g12a.c              | 350 ++++++++++++++++++++++++++
>>  drivers/clk/meson/g12a.h              |  22 +-
>>  include/dt-bindings/clock/g12a-clkc.h |   1 +
>>  3 files changed, 372 insertions(+), 1 deletion(-)
>>
> 
> With the small naming comment on patch 2
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 

I fixed the naming while applying on next/headers for patch 1, next/drivers for patch 2

Neil