* [PATCH v2] clk: Add fractional scale clock support
@ 2016-06-20 21:31 Hoan Tran
[not found] ` <20160630202358.GC27880@codeaurora.org>
0 siblings, 1 reply; 7+ messages in thread
From: Hoan Tran @ 2016-06-20 21:31 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-kernel, linux-clk, lho, Duc Dang, Hoan Tran
This patch adds fractional scale clock support.
Fractional scale clock is implemented for a single register field.
Output rate = parent_rate * scale / denominator
For example, for 1 / 8 fractional scale, denominator will be 8 and scale
will be computed and programmed accordingly.
v2
* Fix compile error by using DIV_ROUND_UP_ULL() macro
* Remove DT binding document
* Remove DT clk_fractional_scale_init() function
v1
* Initial
Signed-off-by: Hoan Tran <hotran@apm.com>
Signed-off-by: Loc Ho <lho@apm.com>
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-fractional-scale.c | 195 +++++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 41 ++++++++
3 files changed, 237 insertions(+)
create mode 100644 drivers/clk/clk-fractional-scale.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dcc5e69..d7deddf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
+obj-$(CONFIG_COMMON_CLK) += clk-fractional-scale.o
obj-$(CONFIG_COMMON_CLK) += clk-gpio.o
ifeq ($(CONFIG_OF), y)
obj-$(CONFIG_COMMON_CLK) += clk-conf.o
diff --git a/drivers/clk/clk-fractional-scale.c b/drivers/clk/clk-fractional-scale.c
new file mode 100644
index 0000000..c4e9e06
--- /dev/null
+++ b/drivers/clk/clk-fractional-scale.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2016 Applied Micro Circuits Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fractional scale clock is implemented for a single register field.
+ *
+ * Output rate = parent_rate * scale / denominator
+ *
+ * For example, for 1/8 fractional scale, denominator will be 8 and scale
+ * will be computed and programmed accordingly.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define to_clk_sf(_hw) container_of(_hw, struct clk_fractional_scale, hw)
+
+static unsigned long clk_fs_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_fractional_scale *fd = to_clk_sf(hw);
+ unsigned long flags = 0;
+ u64 ret, scale;
+ u32 val;
+
+ if (fd->lock)
+ spin_lock_irqsave(fd->lock, flags);
+ else
+ __acquire(fd->lock);
+
+ val = clk_readl(fd->reg);
+
+ if (fd->lock)
+ spin_unlock_irqrestore(fd->lock, flags);
+ else
+ __release(fd->lock);
+
+ ret = (u64) parent_rate;
+
+ scale = (val & fd->mask) >> fd->shift;
+ if (fd->flags & CLK_FRACTIONAL_SCALE_INVERTED)
+ scale = fd->denom - scale;
+ else
+ scale++;
+
+ /* freq = parent_rate * scaler / denom */
+ do_div(ret, fd->denom);
+ ret *= scale;
+ if (ret == 0)
+ ret = (u64) parent_rate;
+
+ return ret;
+}
+
+static long clk_fs_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_fractional_scale *fd = to_clk_sf(hw);
+ u64 ret, scale;
+
+ if (!rate || rate >= *parent_rate)
+ return *parent_rate;
+
+ /* freq = parent_rate * scaler / denom */
+ ret = rate * fd->denom;
+ scale = DIV_ROUND_UP_ULL(ret, *parent_rate);
+
+ ret = (u64) *parent_rate * scale;
+ do_div(ret, fd->denom);
+
+ return ret;
+}
+
+static int clk_fs_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_fractional_scale *fd = to_clk_sf(hw);
+ unsigned long flags = 0;
+ u64 scale, ret;
+ u32 val;
+
+ /*
+ * Compute the scaler:
+ *
+ * freq = parent_rate * scaler / denom, or
+ * scaler = freq * denom / parent_rate
+ */
+ ret = rate * fd->denom;
+ scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate);
+
+ /* Check if inverted */
+ if (fd->flags & CLK_FRACTIONAL_SCALE_INVERTED)
+ scale = fd->denom - scale;
+ else
+ scale--;
+
+ if (fd->lock)
+ spin_lock_irqsave(fd->lock, flags);
+ else
+ __acquire(fd->lock);
+
+ val = clk_readl(fd->reg);
+ val &= ~fd->mask;
+ val |= (scale << fd->shift);
+ clk_writel(val, fd->reg);
+
+ if (fd->lock)
+ spin_unlock_irqrestore(fd->lock, flags);
+ else
+ __release(fd->lock);
+
+ return 0;
+}
+
+const struct clk_ops clk_fractional_scale_ops = {
+ .recalc_rate = clk_fs_recalc_rate,
+ .round_rate = clk_fs_round_rate,
+ .set_rate = clk_fs_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fractional_scale_ops);
+
+struct clk_hw *clk_hw_register_fractional_scale(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u64 denom,
+ u32 clk_flags, spinlock_t *lock)
+{
+ struct clk_fractional_scale *fd;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fractional_scale_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ fd->reg = reg;
+ fd->shift = shift;
+ fd->mask = (BIT(width) - 1) << shift;
+ fd->denom = denom;
+ fd->flags = clk_flags;
+ fd->lock = lock;
+ fd->hw.init = &init;
+
+ hw = &fd->hw;
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(fd);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+EXPORT_SYMBOL_GPL(clk_hw_register_fractional_scale);
+
+struct clk *clk_register_fractional_scale(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u64 denom,
+ u32 clk_flags, spinlock_t *lock)
+{
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_fractional_scale(dev, name, parent_name, flags,
+ reg, shift, width, denom,
+ clk_flags, lock);
+ if (IS_ERR(hw))
+ return ERR_CAST(hw);
+
+ return hw->clk;
+}
+EXPORT_SYMBOL_GPL(clk_register_fractional_scale);
+
+void clk_hw_unregister_fractional_scale(struct clk_hw *hw)
+{
+ struct clk_fractional_scale *fd;
+
+ fd = to_clk_sf(hw);
+
+ clk_hw_unregister(hw);
+ kfree(fd);
+}
+EXPORT_SYMBOL_GPL(clk_hw_unregister_fractional_scale);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 0c72204..7d33bc0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -578,6 +578,47 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
/**
+ * struct clk_fractional_scale - Fractional scale clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register containing the fractional scale multiplier (scaler)
+ * @shift: shift to the unit bit field
+ * @width: width of the unit bit field
+ * @denom: 1/denominator unit
+ * @lock: register lock
+ *
+ * Clock with fractional scale affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRACTIONAL_SCALE_INVERTED - by default the scaler is the value read
+ * from the register plus one. For example,
+ * 0 for (0 + 1) / denom,
+ * 1 for (1 + 1) / denom and etc.
+ * If this flag is set, it is
+ * 0 for (denom - 0) / denom,
+ * 1 for (denom - 1) / denom and etc.
+ */
+
+struct clk_fractional_scale {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 shift;
+ u32 mask;
+ u64 denom;
+ u32 flags;
+ spinlock_t *lock;
+};
+
+#define CLK_FRACTIONAL_SCALE_INVERTED BIT(0)
+
+extern const struct clk_ops clk_fractional_scale_ops;
+struct clk *clk_register_fractional_scale(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u64 denom,
+ u32 clk_flags, spinlock_t *lock);
+
+
+/**
* struct clk_multiplier - adjustable multiplier clock
*
* @hw: handle between common and hardware-specific interfaces
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
[not found] ` <CAFHUOYxS-aZGE-W8Oaop6hgfvd6MsvJ_N+GHTYdOzQZhH7hUPA@mail.gmail.com>
@ 2016-07-01 18:38 ` Stephen Boyd
2016-07-02 0:09 ` Hoan Tran
0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2016-07-01 18:38 UTC (permalink / raw)
To: Hoan Tran; +Cc: Michael Turquette, linux-kernel, linux-clk, Duc Dang, lho
Sorry I replied offlist before. Pressed the wrong key.
On 06/30, Hoan Tran wrote:
> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> >
> > How is this different from clk-fractional-divider.c?
> >
>
> This is a driver which clock output is multiplied with a fixed fractional
> scale (denominator).
> A field inside a register is used to configure the multiplier.
>
> Example: With fractional scale is 1/8.
> Freq_out = Freq_parent * multiplier * (1/8)
>
> For fractional-divider, there are 2 fields of a register are used which
> - A field for numerator
> - A field for denominator
> Freq_out = Freq_parent * numerator / denominator
>
Ok so the difference is that the denominator is a fixed value?
Perhaps that can be modeled as a clk-multiplier that is used as
the only parent of a fixed divider? Or we can add a flag to the
clk-fractional-divider code to handle this minor difference.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
2016-07-01 18:38 ` Stephen Boyd
@ 2016-07-02 0:09 ` Hoan Tran
2016-07-20 18:36 ` Hoan Tran
0 siblings, 1 reply; 7+ messages in thread
From: Hoan Tran @ 2016-07-02 0:09 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, lkml, linux-clk, Duc Dang, Loc Ho
Hi Stephen,
On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> Sorry I replied offlist before. Pressed the wrong key.
>
> On 06/30, Hoan Tran wrote:
>> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >
>> > How is this different from clk-fractional-divider.c?
>> >
>>
>> This is a driver which clock output is multiplied with a fixed fractional
>> scale (denominator).
>> A field inside a register is used to configure the multiplier.
>>
>> Example: With fractional scale is 1/8.
>> Freq_out = Freq_parent * multiplier * (1/8)
>>
>> For fractional-divider, there are 2 fields of a register are used which
>> - A field for numerator
>> - A field for denominator
>> Freq_out = Freq_parent * numerator / denominator
>>
>
> Ok so the difference is that the denominator is a fixed value?
The major difference is a fixed denominator.
Another difference is:
In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below
Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.
> Perhaps that can be modeled as a clk-multiplier that is used as
> the only parent of a fixed divider?
Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
model as a clk-multiplier. And how to pass the fixed denominator into
a clk-multiplier.
> Or we can add a flag to the
> clk-fractional-divider code to handle this minor difference.
This driver is used 2 register fields for numerator, denominator and
calculates both of them.
Do you think I can integrate this fractional scale into it ?
Thanks
Hoan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
2016-07-02 0:09 ` Hoan Tran
@ 2016-07-20 18:36 ` Hoan Tran
2016-08-08 23:40 ` Hoan Tran
0 siblings, 1 reply; 7+ messages in thread
From: Hoan Tran @ 2016-07-20 18:36 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, lkml, linux-clk, Duc Dang, Loc Ho
On Fri, Jul 1, 2016 at 5:09 PM, Hoan Tran <hotran@apm.com> wrote:
>
> Hi Stephen,
>
> On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> > Sorry I replied offlist before. Pressed the wrong key.
> >
> > On 06/30, Hoan Tran wrote:
> >> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> >> >
> >> > How is this different from clk-fractional-divider.c?
> >> >
> >>
> >> This is a driver which clock output is multiplied with a fixed fractional
> >> scale (denominator).
> >> A field inside a register is used to configure the multiplier.
> >>
> >> Example: With fractional scale is 1/8.
> >> Freq_out = Freq_parent * multiplier * (1/8)
> >>
> >> For fractional-divider, there are 2 fields of a register are used which
> >> - A field for numerator
> >> - A field for denominator
> >> Freq_out = Freq_parent * numerator / denominator
> >>
> >
> > Ok so the difference is that the denominator is a fixed value?
>
> The major difference is a fixed denominator.
> Another difference is:
> In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below
>
> Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.
>
> > Perhaps that can be modeled as a clk-multiplier that is used as
> > the only parent of a fixed divider?
>
> Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
> model as a clk-multiplier. And how to pass the fixed denominator into
> a clk-multiplier.
>
> > Or we can add a flag to the
> > clk-fractional-divider code to handle this minor difference.
>
> This driver is used 2 register fields for numerator, denominator and
> calculates both of them.
> Do you think I can integrate this fractional scale into it ?
>
> Thanks
> Hoan
>
Hi Stephen,
Do you have any comments ?
Thanks
Hoan
>
> >
> > --
> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> > a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
2016-07-20 18:36 ` Hoan Tran
@ 2016-08-08 23:40 ` Hoan Tran
2016-08-16 0:14 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Hoan Tran @ 2016-08-08 23:40 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, lkml, linux-clk, Duc Dang, Loc Ho
On Wed, Jul 20, 2016 at 11:36 AM, Hoan Tran <hotran@apm.com> wrote:
> On Fri, Jul 1, 2016 at 5:09 PM, Hoan Tran <hotran@apm.com> wrote:
>>
>> Hi Stephen,
>>
>> On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> > Sorry I replied offlist before. Pressed the wrong key.
>> >
>> > On 06/30, Hoan Tran wrote:
>> >> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >> >
>> >> > How is this different from clk-fractional-divider.c?
>> >> >
>> >>
>> >> This is a driver which clock output is multiplied with a fixed fractional
>> >> scale (denominator).
>> >> A field inside a register is used to configure the multiplier.
>> >>
>> >> Example: With fractional scale is 1/8.
>> >> Freq_out = Freq_parent * multiplier * (1/8)
>> >>
>> >> For fractional-divider, there are 2 fields of a register are used which
>> >> - A field for numerator
>> >> - A field for denominator
>> >> Freq_out = Freq_parent * numerator / denominator
>> >>
>> >
>> > Ok so the difference is that the denominator is a fixed value?
>>
>> The major difference is a fixed denominator.
>> Another difference is:
>> In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below
>>
>> Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.
>>
>> > Perhaps that can be modeled as a clk-multiplier that is used as
>> > the only parent of a fixed divider?
>>
>> Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
>> model as a clk-multiplier. And how to pass the fixed denominator into
>> a clk-multiplier.
>>
>> > Or we can add a flag to the
>> > clk-fractional-divider code to handle this minor difference.
>>
>> This driver is used 2 register fields for numerator, denominator and
>> calculates both of them.
>> Do you think I can integrate this fractional scale into it ?
>>
>> Thanks
>> Hoan
>>
>
> Hi Stephen,
>
> Do you have any comments ?
>
> Thanks
> Hoan
>
>
>>
>> >
>> > --
>> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> > a Linux Foundation Collaborative Project
Hi Stephen,
Do you have any comments or suggestions on this patch ?
Thanks
Hoan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
2016-08-08 23:40 ` Hoan Tran
@ 2016-08-16 0:14 ` Stephen Boyd
2016-08-16 17:39 ` Hoan Tran
0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2016-08-16 0:14 UTC (permalink / raw)
To: Hoan Tran; +Cc: Michael Turquette, lkml, linux-clk, Duc Dang, Loc Ho
Sorry I was away for some time.
On 08/08, Hoan Tran wrote:
> On Wed, Jul 20, 2016 at 11:36 AM, Hoan Tran <hotran@apm.com> wrote:
> > On Fri, Jul 1, 2016 at 5:09 PM, Hoan Tran <hotran@apm.com> wrote:
> >>
> >> Hi Stephen,
> >>
> >> On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> >> > Sorry I replied offlist before. Pressed the wrong key.
> >> >
> >> > On 06/30, Hoan Tran wrote:
> >> >> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> >> >> >
> >> >> > How is this different from clk-fractional-divider.c?
> >> >> >
> >> >>
> >> >> This is a driver which clock output is multiplied with a fixed fractional
> >> >> scale (denominator).
> >> >> A field inside a register is used to configure the multiplier.
> >> >>
> >> >> Example: With fractional scale is 1/8.
> >> >> Freq_out = Freq_parent * multiplier * (1/8)
> >> >>
> >> >> For fractional-divider, there are 2 fields of a register are used which
> >> >> - A field for numerator
> >> >> - A field for denominator
> >> >> Freq_out = Freq_parent * numerator / denominator
> >> >>
> >> >
> >> > Ok so the difference is that the denominator is a fixed value?
> >>
> >> The major difference is a fixed denominator.
> >> Another difference is:
> >> In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below
> >>
> >> Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.
> >>
> >> > Perhaps that can be modeled as a clk-multiplier that is used as
> >> > the only parent of a fixed divider?
> >>
> >> Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
> >> model as a clk-multiplier. And how to pass the fixed denominator into
> >> a clk-multiplier.
Would it be possible to add a flag to clk-multiplier to handle
the inverted case? I haven't seen anyone else with hardware like
that though, so perhaps the implementation should just go into
the vendor specific clk driver instead of being written
as a "basic clk type".
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] clk: Add fractional scale clock support
2016-08-16 0:14 ` Stephen Boyd
@ 2016-08-16 17:39 ` Hoan Tran
0 siblings, 0 replies; 7+ messages in thread
From: Hoan Tran @ 2016-08-16 17:39 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, lkml, linux-clk, Duc Dang, Loc Ho
On Mon, Aug 15, 2016 at 5:14 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> Sorry I was away for some time.
>
> On 08/08, Hoan Tran wrote:
>> On Wed, Jul 20, 2016 at 11:36 AM, Hoan Tran <hotran@apm.com> wrote:
>> > On Fri, Jul 1, 2016 at 5:09 PM, Hoan Tran <hotran@apm.com> wrote:
>> >>
>> >> Hi Stephen,
>> >>
>> >> On Fri, Jul 1, 2016 at 11:38 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >> > Sorry I replied offlist before. Pressed the wrong key.
>> >> >
>> >> > On 06/30, Hoan Tran wrote:
>> >> >> On Thu, Jun 30, 2016 at 1:23 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> >> >> >
>> >> >> > How is this different from clk-fractional-divider.c?
>> >> >> >
>> >> >>
>> >> >> This is a driver which clock output is multiplied with a fixed fractional
>> >> >> scale (denominator).
>> >> >> A field inside a register is used to configure the multiplier.
>> >> >>
>> >> >> Example: With fractional scale is 1/8.
>> >> >> Freq_out = Freq_parent * multiplier * (1/8)
>> >> >>
>> >> >> For fractional-divider, there are 2 fields of a register are used which
>> >> >> - A field for numerator
>> >> >> - A field for denominator
>> >> >> Freq_out = Freq_parent * numerator / denominator
>> >> >>
>> >> >
>> >> > Ok so the difference is that the denominator is a fixed value?
>> >>
>> >> The major difference is a fixed denominator.
>> >> Another difference is:
>> >> In case CLK_FRACTIONAL_SCALE_INVERTED=1, the freq_out is calculated as below
>> >>
>> >> Freq_out = Freq_parent * (fixed_denominator - multiplier) / fixed_denominator.
>> >>
>> >> > Perhaps that can be modeled as a clk-multiplier that is used as
>> >> > the only parent of a fixed divider?
>> >>
>> >> Because of CLK_FRACTIONAL_SCALE_INVERTED flag, I don't know how to
>> >> model as a clk-multiplier. And how to pass the fixed denominator into
>> >> a clk-multiplier.
>
> Would it be possible to add a flag to clk-multiplier to handle
> the inverted case? I haven't seen anyone else with hardware like
> that though, so perhaps the implementation should just go into
> the vendor specific clk driver instead of being written
> as a "basic clk type".
Yes, I'll move it into our clk-xgene driver.
Thanks
Hoan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
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2016-06-20 21:31 [PATCH v2] clk: Add fractional scale clock support Hoan Tran
[not found] ` <20160630202358.GC27880@codeaurora.org>
[not found] ` <CAFHUOYxS-aZGE-W8Oaop6hgfvd6MsvJ_N+GHTYdOzQZhH7hUPA@mail.gmail.com>
2016-07-01 18:38 ` Stephen Boyd
2016-07-02 0:09 ` Hoan Tran
2016-07-20 18:36 ` Hoan Tran
2016-08-08 23:40 ` Hoan Tran
2016-08-16 0:14 ` Stephen Boyd
2016-08-16 17:39 ` Hoan Tran
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