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Wed, 15 May 2019 23:48:04 -0700 (PDT) MIME-Version: 1.0 References: <20190515233234.22990-1-bjorn.andersson@linaro.org> In-Reply-To: <20190515233234.22990-1-bjorn.andersson@linaro.org> From: Vivek Gautam Date: Thu, 16 May 2019 12:17:53 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] iommu: io-pgtable: Support non-coherent page tables To: Bjorn Andersson Cc: Will Deacon , Robin Murphy , Joerg Roedel , linux-arm-msm , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," , Vivek Gautam , open list , Linux ARM Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 16, 2019 at 5:03 AM Bjorn Andersson wrote: > > Describe the memory related to page table walks as non-cachable for iommu > instances that are not DMA coherent. > > Signed-off-by: Bjorn Andersson > --- > drivers/iommu/io-pgtable-arm.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c > index 4e21efbc4459..68ff22ffd2cb 100644 > --- a/drivers/iommu/io-pgtable-arm.c > +++ b/drivers/iommu/io-pgtable-arm.c > @@ -803,9 +803,15 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) > return NULL; > > /* TCR */ > - reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | > - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); > + if (cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) { > + reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | > + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); > + } else { > + reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | > + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT); > + } This looks okay to me based on the discussion that we had on a similar patch that I posted. So, Reviewed-by: Vivek Gautam [1] https://lore.kernel.org/patchwork/patch/1032939/ Thanks & regards Vivek > > switch (ARM_LPAE_GRANULE(data)) { > case SZ_4K: > -- > 2.18.0 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation