From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752610AbdGJGme (ORCPT ); Mon, 10 Jul 2017 02:42:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48170 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750847AbdGJGmc (ORCPT ); Mon, 10 Jul 2017 02:42:32 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6873160FF4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org MIME-Version: 1.0 In-Reply-To: <20170710034057.o5tha22rlllbxu3y@rob-hp-laptop> References: <1499333825-7658-1-git-send-email-vivek.gautam@codeaurora.org> <1499333825-7658-7-git-send-email-vivek.gautam@codeaurora.org> <20170710034057.o5tha22rlllbxu3y@rob-hp-laptop> From: Vivek Gautam Date: Mon, 10 Jul 2017 12:12:29 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V4 6/6] iommu/arm-smmu: Add support for qcom,msm8996-smmu-v2 clocks To: Rob Herring Cc: joro@8bytes.org, robin.murphy@arm.com, Mark Rutland , Will Deacon , Marek Szyprowski , Stephen Boyd , robdclark@gmail.com, iommu@lists.linux-foundation.org, "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, sricharan@codeaurora.org, Stanimir Varbanov , architt@codeaurora.org, "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On Mon, Jul 10, 2017 at 9:10 AM, Rob Herring wrote: > On Thu, Jul 06, 2017 at 03:07:05PM +0530, Vivek Gautam wrote: >> qcom,msm8996-smmu-v2 is an arm,smmu-v2 implementation with >> specific clock and power requirements. This smmu core is used >> with multiple masters on msm8996, viz. mdss, video, etc. >> Add bindings for the same. >> >> Signed-off-by: Vivek Gautam >> --- >> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 18 ++++++++++++++++++ >> drivers/iommu/arm-smmu.c | 13 +++++++++++++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt >> index 00331752d355..5d8e79775fae 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt >> @@ -17,6 +17,7 @@ conditions. >> "arm,mmu-401" >> "arm,mmu-500" >> "cavium,smmu-v2" >> + "qcom,msm8996-smmu-v2" >> >> depending on the particular implementation and/or the >> version of the architecture implemented. >> @@ -74,11 +75,16 @@ conditions. >> - clock-names: Should be "tcu" and "iface" for "arm,mmu-400", >> "arm,mmu-401" and "arm,mmu-500" >> >> + Should be "bus", and "iface" for "qcom,msm8996-smmu-v2" >> + implementation. >> + >> "tcu" clock is required for smmu's register access using the >> programming interface and ptw for downstream bus access. This >> clock is also used for access to the TBU connected to the >> master locally. Sometimes however, TBU is clocked along with >> the master. >> + "bus" clock for "qcom,msm8996-smmu-v2" is requierd for downstream > > s/requierd/required/ sure, will correct it. > >> + bus access and for the smmu ptw. >> >> "iface" clock is required to access the TCU's programming >> interface, apart from the "tcu" clock. >> @@ -161,3 +167,15 @@ conditions. >> iommu-map = <0 &smmu3 0 0x400>; >> ... >> }; >> + >> + /* Qcom's arm,smmu-v2 implementation for msm8996 */ >> + smmu4: iommu { >> + compatible = "qcom,msm8996-smmu-v2"; > > No registers? It does have registers. Will add the complete binding example. Thank you for the review. Best Regards Vivek [snip] -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project