From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 167FDC4332F for ; Fri, 29 Oct 2021 16:55:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE2A8611AD for ; Fri, 29 Oct 2021 16:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230204AbhJ2Q6V (ORCPT ); Fri, 29 Oct 2021 12:58:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbhJ2Q6T (ORCPT ); Fri, 29 Oct 2021 12:58:19 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 009D8C061767; Fri, 29 Oct 2021 09:55:50 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id d5so1899253wrc.1; Fri, 29 Oct 2021 09:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qw9eUIKKFJxw16iLE6OQRzEo/+G/I/ws7yCWh747U2o=; b=C33kUFoG9cb+/x4ofa7cyBAQz8S60FQ2WR7DHWWhEHMtAldrpfZ+Kz1wQR24R9ycHV doAAwbMrY7jOyC5XLNlKpO91th966/kivL9zrq/piWrb26fJgxUQv1F9O61VH6kdBNzt +6BL9AF6JJ7XnWdS8opuTknLO53PvYwsRmoJsf0qkj71r4Nsr/8m2M46CoUEwAhLvlrL toJ0YR7QeeuofH8MmTcQWH8qKHbGo31SV5ZE/Rvq8ao2kNXNWCfHuq8NkAP0IpCL4pMp /JY4GuanuhM+eVhfdlG4qCdWSn4rJnYdNCd5AepgKcG4v1vIX6i+IVSSA4qkGaaHldmL 8DQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qw9eUIKKFJxw16iLE6OQRzEo/+G/I/ws7yCWh747U2o=; b=Zl+zGCXpHkron1eVEU61sjDCoa+QM0qtHQuTbg8G2PBsEuiUfhSeGIDyrlqLR4kfhp pfY+027YTPr1nuS4xLJVIEQNSoKs/R3mk20fGPxf2jD3cC9kLDwwDHKTyHJ6TfY6TCGy F4JQIKue+qyYOoqxiqYnpyTvEjglfUU9j6AyEhguvyfRcEMYnRxsw+vtB+fDjahJ1HVA pzO+ykloEtmr/r8yndkcCc2BYjCnvM1Ed1k94kACUftUjzENSo1A9K43FxX8kEaQ1qkq EiZV5a695TPZTYuHy5C13JnKUZy5xIkYeKSqb6VtyU+X5RqkvmBSFbjLkKnTMvSabqTI vfBg== X-Gm-Message-State: AOAM531l6APn3e8K30vOquW3ApojHXJw7YNxiee80uSil2XmL8jZYRiU 4YmktTNhd5eKGiLpaYiJ10PR3zZclMNwJPNFVFU= X-Google-Smtp-Source: ABdhPJw9Owdy8eqtoHZ5MoZTgP0TClCRwRmVH+TYJJzZNR9zxAAgQQGskCuZ+tXGL5hUOLwwgf46l8LFmPR+RPpxbVo= X-Received: by 2002:a5d:64c5:: with SMTP id f5mr5832309wri.222.1635526549506; Fri, 29 Oct 2021 09:55:49 -0700 (PDT) MIME-Version: 1.0 References: <20211026181240.213806-1-paul@crapouillou.net> <20211026181240.213806-6-paul@crapouillou.net> In-Reply-To: <20211026181240.213806-6-paul@crapouillou.net> From: Christophe Branchereau Date: Fri, 29 Oct 2021 18:55:38 +0200 Message-ID: Subject: Re: [RESEND PATCH v3 5/6] drm/ingenic: Upload palette before frame To: Paul Cercueil Cc: David Airlie , Daniel Vetter , Laurent Pinchart , Sam Ravnborg , "H . Nikolaus Schaller" , Paul Boddie , list@opendingux.net, linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Christophe Branchereau On Tue, Oct 26, 2021 at 8:13 PM Paul Cercueil wrote: > > When using C8 color mode, make sure that the palette is always uploaded > before a frame; otherwise the very first frame will have wrong colors. > > Do that by changing the link order of the DMA descriptors. > > v3: Fix ingenic_drm_get_new_priv_state() called instead of > ingenic_drm_get_priv_state() > > Signed-off-by: Paul Cercueil > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 53 ++++++++++++++++++++--- > 1 file changed, 47 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index cbc76cede99e..a5e2880e07a1 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -66,6 +66,7 @@ struct jz_soc_info { > > struct ingenic_drm_private_state { > struct drm_private_state base; > + bool use_palette; > }; > > struct ingenic_drm { > @@ -113,6 +114,30 @@ to_ingenic_drm_priv_state(struct drm_private_state *state) > return container_of(state, struct ingenic_drm_private_state, base); > } > > +static struct ingenic_drm_private_state * > +ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) > +{ > + struct drm_private_state *priv_state; > + > + priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); > + if (IS_ERR(priv_state)) > + return ERR_CAST(priv_state); > + > + return to_ingenic_drm_priv_state(priv_state); > +} > + > +static struct ingenic_drm_private_state * > +ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) > +{ > + struct drm_private_state *priv_state; > + > + priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); > + if (!priv_state) > + return NULL; > + > + return to_ingenic_drm_priv_state(priv_state); > +} > + > static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) > { > switch (reg) { > @@ -183,11 +208,18 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, > struct drm_atomic_state *state) > { > struct ingenic_drm *priv = drm_crtc_get_priv(crtc); > + struct ingenic_drm_private_state *priv_state; > + unsigned int next_id; > + > + priv_state = ingenic_drm_get_priv_state(priv, state); > + if (WARN_ON(IS_ERR(priv_state))) > + return; > > regmap_write(priv->map, JZ_REG_LCD_STATE, 0); > > - /* Set address of our DMA descriptor chain */ > - regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0)); > + /* Set addresses of our DMA descriptor chains */ > + next_id = priv_state->use_palette ? HWDESC_PALETTE : 0; > + regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id)); > regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); > > regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > @@ -393,6 +425,7 @@ static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, > struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, > plane); > struct ingenic_drm *priv = drm_device_get_priv(plane->dev); > + struct ingenic_drm_private_state *priv_state; > struct drm_crtc_state *crtc_state; > struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; > int ret; > @@ -405,6 +438,10 @@ static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, > if (WARN_ON(!crtc_state)) > return -EINVAL; > > + priv_state = ingenic_drm_get_priv_state(priv, state); > + if (IS_ERR(priv_state)) > + return PTR_ERR(priv_state); > + > ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, > DRM_PLANE_HELPER_NO_SCALING, > DRM_PLANE_HELPER_NO_SCALING, > @@ -423,6 +460,9 @@ static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, > (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) > return -EINVAL; > > + priv_state->use_palette = new_plane_state->fb && > + new_plane_state->fb->format->format == DRM_FORMAT_C8; > + > /* > * Require full modeset if enabling or disabling a plane, or changing > * its position, size or depth. > @@ -583,6 +623,7 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, > struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); > struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); > unsigned int width, height, cpp, next_id, plane_id; > + struct ingenic_drm_private_state *priv_state; > struct drm_crtc_state *crtc_state; > struct ingenic_dma_hwdesc *hwdesc; > dma_addr_t addr; > @@ -600,19 +641,19 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, > height = newstate->src_h >> 16; > cpp = newstate->fb->format->cpp[0]; > > - hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; > + priv_state = ingenic_drm_get_new_priv_state(priv, state); > + next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; > > + hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; > hwdesc->addr = addr; > hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); > + hwdesc->next = dma_hwdesc_addr(priv, next_id); > > if (drm_atomic_crtc_needs_modeset(crtc_state)) { > fourcc = newstate->fb->format->format; > > ingenic_drm_plane_config(priv->dev, plane, fourcc); > > - next_id = fourcc == DRM_FORMAT_C8 ? HWDESC_PALETTE : 0; > - priv->dma_hwdescs->hwdesc[0].next = dma_hwdesc_addr(priv, next_id); > - > crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; > } > > -- > 2.33.0 >