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bh=gOFfzzfB3icWGJyf7fd7qOAkUBx8OfOCfNvo7lnaGYw=; b=KaPQ8yCpIZ4VrkBJ3JUUBFsGOd0J0jm//z3S+O2P8t8b3NHuyBda5R3ltSbHARyAnp zSmx8VxkkFOJxS85M14ss/EV5hmlMVxPcp0c1XcXicVsZGDqf39qz9agqq6nmkFgTXDd 1cWp3R69floVe3IyJRJd4/8pKBUUgy6IXjxM0nCbjtavfvnNHWqtUeYG+W7mzdYUGrKs ry7M53etSqZjQGHTS7mYcwBQ4ZVmSbzAcTiM9KoD2CW8ua+7NXo9r7N+vDwoLH5jsPE2 iD+dT1xdjCDJqlVgZXsnRFOLY2h9YyUMbyXWulaBG0f1lh6eSOso04y8QY+SmUPXAMmK 3p8A== X-Gm-Message-State: AOAM533M5M1gaoUMS1OYMV6nyTfeVdmeOuWNUmk7dcCjLUaBTTmlvdAi vLC0V1biw/w9pfkLjkaISAUfRc2qsrJ98mFvAui+mg== X-Google-Smtp-Source: ABdhPJxQYINbrnkbID4F3k8iJOHCoCXHacOfFXlPSJpossaqYKp4Q8nwrksZOualbPoua2Grp4gvm+09tDaR1QbMJAU= X-Received: by 2002:a17:90a:c394:: with SMTP id h20mr20745388pjt.222.1624629096164; Fri, 25 Jun 2021 06:51:36 -0700 (PDT) MIME-Version: 1.0 References: <20210616141107.291430-1-robert.foss@linaro.org> <20210616141107.291430-6-robert.foss@linaro.org> <20210624211844.GA1997615@robh.at.kernel.org> In-Reply-To: <20210624211844.GA1997615@robh.at.kernel.org> From: Robert Foss Date: Fri, 25 Jun 2021 15:51:24 +0200 Message-ID: Subject: Re: [RFC v1 05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings To: Rob Herring Cc: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek , Taniya Das , MSM , "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , Vinod Koul Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 24 Jun 2021 at 23:18, Rob Herring wrote: > > On Wed, Jun 16, 2021 at 04:11:01PM +0200, Robert Foss wrote: > > Add device tree bindings for display clock controller for > > Qualcomm Technology Inc's SM8350 SoC. > > > > Signed-off-by: Robert Foss > > --- > > .../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +- > > .../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +++++++++++++++++++ > > 2 files changed, 81 insertions(+), 2 deletions(-) > > create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h > > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > index 0cdf53f41f84..c10eefd024f6 100644 > > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > @@ -4,24 +4,26 @@ > > $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# > > $schema: http://devicetree.org/meta-schemas/core.yaml# > > > > -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 > > +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 > > > > maintainers: > > - Jonathan Marek > > > > description: | > > Qualcomm display clock control module which supports the clocks, resets and > > - power domains on SM8150 and SM8250. > > + power domains on SM8150, SM8250 and SM8350. > > > > See also: > > dt-bindings/clock/qcom,dispcc-sm8150.h > > dt-bindings/clock/qcom,dispcc-sm8250.h > > + dt-bindings/clock/qcom,dispcc-sm8350.h > > > > properties: > > compatible: > > enum: > > - qcom,sm8150-dispcc > > - qcom,sm8250-dispcc > > + - qcom,sm8350-dispcc > > > > clocks: > > items: > > diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h > > new file mode 100644 > > index 000000000000..361ef27de585 > > --- /dev/null > > +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h > > @@ -0,0 +1,77 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > I'm tired of saying this for QCom bindings given it's been QCom I've > gotten complaints on DT licensing, but dual license please. Spread the > word. > > I'm sure if someone audited licenses of headers and dts files they'd > find a mess. Thanks for pointing this out. I'll keep an eye out and change it to (GPL-2.0-only OR BSD-2-Clause).