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From: Jann Horn <jannh@google.com>
To: "Harry Wentland" <harry.wentland@amd.com>,
	"Leo Li" <sunpeng.li@amd.com>,
	amd-gfx@lists.freedesktop.org,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	"the arch/x86 maintainers" <x86@kernel.org>,
	kernel list <linux-kernel@vger.kernel.org>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	Andy Lutomirski <luto@kernel.org>
Subject: AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection
Date: Thu, 2 Apr 2020 04:34:52 +0200	[thread overview]
Message-ID: <CAG48ez2Sx4ELkM94aD_h_J7K7KBOeuGmvZLKRkg3n_f2WoZ_cg@mail.gmail.com> (raw)

[x86 folks in CC so that they can chime in on the precise rules for this stuff]

Hi!

I noticed that several makefiles under drivers/gpu/drm/amd/display/dc/
turn on floating-point instructions in the compiler flags
(-mhard-float, -msse and -msse2) in order to make the "float" and
"double" types usable from C code without requiring helper functions.

However, as far as I know, code running in normal kernel context isn't
allowed to use floating-point registers without special protection
using helpers like kernel_fpu_begin() and kernel_fpu_end() (which also
require that the protected code never blocks). If you violate that
rule, that can lead to various issues - among other things, I think
the kernel will clobber userspace FPU register state, and I think the
kernel code can blow up if a context switch happens at the wrong time,
since in-kernel task switches don't preserve FPU state.

Is there some hidden trick I'm missing that makes it okay to use FPU
registers here?

I would try testing this, but unfortunately none of the AMD devices I
have here have the appropriate graphics hardware...

             reply	other threads:[~2020-04-02  2:35 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-02  2:34 Jann Horn [this message]
2020-04-02  7:33 ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Christian König
2020-04-02  7:56   ` Jann Horn
2020-04-02  9:36     ` Thomas Gleixner
2020-04-02 14:50       ` Jann Horn
2020-04-02 14:13   ` Peter Zijlstra
2020-04-03  5:28     ` Masami Hiramatsu
2020-04-03 11:21       ` Peter Zijlstra
2020-04-04  3:08         ` Masami Hiramatsu
2020-04-04  3:15           ` Randy Dunlap
2020-04-04  8:32             ` Masami Hiramatsu
2020-04-04 14:32           ` Peter Zijlstra
2020-04-05  3:19             ` Masami Hiramatsu
2020-04-06 10:21               ` Peter Zijlstra
2020-04-07  9:50                 ` Masami Hiramatsu
2020-04-07 11:15                   ` Peter Zijlstra
2020-04-07 15:41                     ` Masami Hiramatsu
2020-04-07 15:43                       ` [PATCH] x86: insn: Add insn_is_fpu() Masami Hiramatsu
2020-04-07 15:54                       ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Peter Zijlstra
2020-04-08  0:31                         ` Masami Hiramatsu
2020-04-08 16:09                         ` [PATCH v2] x86: insn: Add insn_is_fpu() Masami Hiramatsu
2020-04-09 14:32                           ` Peter Zijlstra
2020-04-09 14:45                             ` Peter Zijlstra
2020-04-10  0:47                             ` Masami Hiramatsu
2020-04-10  1:22                             ` [PATCH v3] " Masami Hiramatsu
2020-04-15  8:23                               ` Masami Hiramatsu
2020-04-15  8:49                             ` [PATCH v4] " Masami Hiramatsu
2020-04-04 14:36           ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Peter Zijlstra
2020-04-05  3:37             ` Masami Hiramatsu
2020-04-09 15:59     ` Peter Zijlstra
2020-04-09 17:09       ` Peter Zijlstra
2020-04-09 18:15         ` Christian König
2020-04-09 20:01           ` Peter Zijlstra
2020-04-10 14:31             ` Christian König
2020-04-15  9:16               ` Peter Zijlstra
2020-04-17 20:27             ` Rodrigo Siqueira
2020-04-17 21:56               ` Peter Zijlstra

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