Re: [PATCH 0/7] iommu: Permit modular builds of ARM SMMU[v3] drivers

[Saravana Kannan <saravanak@google.com>]

On Mon, Nov 4, 2019 at 4:16 AM John Garry <john.garry@huawei.com> wrote:
>
> On 01/11/2019 21:13, Saravana Kannan wrote:
> > On Fri, Nov 1, 2019 at 3:28 AM John Garry <john.garry@huawei.com> wrote:
> >>
> >> On 31/10/2019 23:34, Saravana Kannan via iommu wrote:
> >>> I looked into the iommu-map property and it shouldn't be too hard to
> >>> add support for it. Looks like we can simply hold off on probing the
> >>> root bridge device till all the iommus in its iommu-map are probed and
> >>> we should be fine.
> >>>
> >>>> I'm also unsure about distro vendors agreeing to a mandatory kernel
> >>>> parameter (of_devlink). Do you plan to eventually enable it by default?
> >>>>
> >>>>> static const struct supplier_bindings of_supplier_bindings[] = {
> >>>>>           { .parse_prop = parse_clocks, },
> >>>>>           { .parse_prop = parse_interconnects, },
> >>>>>           { .parse_prop = parse_regulators, },
> >>>>> +        { .parse_prop = parse_iommus, },
> >>>>>           {},
> >>>>> };
> >>>>>
> >>>>> I plan to upstream this pretty soon, but I have other patches in
> >>>>> flight that touch the same file and I'm waiting for those to get
> >>>>> accepted. I also want to clean up the code a bit to reduce some
> >>>>> repetition before I add support for more bindings.
> >>>> I'm also wondering about ACPI support.
> >>> I'd love to add ACPI support too, but I have zero knowledge of ACPI.
> >>> I'd be happy to help anyone who wants to add ACPI support that allows
> >>> ACPI to add device links.
> >>
> >> If possible to add, that may be useful for remedying this:
> >>
> >> https://lore.kernel.org/linux-iommu/9625faf4-48ef-2dd3-d82f-931d9cf26976@huawei.com/
> >
> > I'm happy that this change might fix that problem, but isn't the
> > problem reported in that thread more to do with child devices getting
> > added before the parent probes successfully? That doesn't make sense
> > to me.
>
> So the pcieport device and then the child device are added in the PCI
> scan, but only some time later do the device drivers probe for these
> devices; so it's not that the that pcieport driver creates the child device.

My lack of PCI knowledge might be showing, but without the pcieport
device itself being functional (I'm assuming this is the PCIe
controller) how does a PCI scan work? In anyway, I understand that all
devices are added at the same time as of today.

> The problem then occurs in that the ordering the of device driver probe
> is such that we have this: pcieport probe + defer (as no IOMMU group
> registered), SMMU probe (registers the IOMMU group), child device probe,
> pcieport really probe.
>
> Can't the piceport driver not add its child devices before it
> > probes successfully? Or more specifically, who adds the child devices
> > of the pcieport before the pcieport itself probes?
>
> The devices are actually added in order pcieport, child device, but not
> really probed in that same order, as above.

Thanks. Got it.

I guess one nice thing that came out of devicetree world is that the
child devices are never probed without the parent probing first (I'm
ignoring the simple-bus devices). It also kinda makes sense to me --
without a USB port device being added and probed, it doesn't make
sense to add the (keyboard, mouse, USB-HDD, etc) devices connected to
the USB port. But this is an orthogonal debate.

-Saravana