From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Enric Balletbo Serra <eballetbo@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
Devicetree List <devicetree@vger.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [v4 4/5] soc: mediatek: pm-domains: Move power status offset to power domain data
Date: Wed, 25 Aug 2021 17:48:58 +0800 [thread overview]
Message-ID: <CAGXv+5Fe6tCaYgn7MUY9g1niyFPx1VwNEidpy3BL0o0a9eoq=A@mail.gmail.com> (raw)
In-Reply-To: <20210823092353.3502-5-chun-jie.chen@mediatek.com>
Hi,
On Mon, Aug 23, 2021 at 5:25 PM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> MT8195 has more than 32 power domains so it needs
> two set of pwr_sta and pwr_sta2nd registers,
> so move the register offset from soc data into power domain data.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
> drivers/soc/mediatek/mt8167-pm-domains.h | 16 +++++++--
> drivers/soc/mediatek/mt8173-pm-domains.h | 22 ++++++++++--
> drivers/soc/mediatek/mt8183-pm-domains.h | 32 +++++++++++++++--
> drivers/soc/mediatek/mt8192-pm-domains.h | 44 ++++++++++++++++++++++--
> drivers/soc/mediatek/mtk-pm-domains.c | 4 +--
> drivers/soc/mediatek/mtk-pm-domains.h | 4 +--
> 6 files changed, 110 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h
> index 15559ddf26e4..4d6c32759606 100644
> --- a/drivers/soc/mediatek/mt8167-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8167-pm-domains.h
[...]
> @@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
> .name = "mfg_async",
> .sta_mask = PWR_STATUS_MFG_ASYNC,
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> + .pwr_sta_offs = SPM_PWR_STATUS,
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> },
This hunk no longer applies due to
http://git.kernel.org/matthias.bgg/c/114956518c85f4e93c298749b35b46b2e78a2ec9
ChenYu
next prev parent reply other threads:[~2021-08-25 9:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210823092353.3502-1-chun-jie.chen@mediatek.com>
2021-08-23 9:23 ` [v4 1/5] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen
2021-08-23 9:23 ` [v4 2/5] soc: mediatek: pm-domains: Add wakeup capacity support in power domain Chun-Jie Chen
2021-08-23 9:23 ` [v4 3/5] soc: mediatek: pm-domains: Remove unused macro Chun-Jie Chen
2021-08-23 9:23 ` [v4 4/5] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen
2021-08-25 9:48 ` Chen-Yu Tsai [this message]
2021-08-23 9:23 ` [v4 5/5] soc: mediatek: pm-domains: Add support for mt8195 Chun-Jie Chen
2021-08-25 10:01 ` Chen-Yu Tsai
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