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From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Rob Herring <robh+dt@kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	LKML <linux-kernel@vger.kernel.org>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>,
	linux-clk@vger.kernel.org,
	Devicetree List <devicetree@vger.kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	Project_Global_Chrome_Upstream_Group 
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [v2 19/24] clk: mediatek: Add MT8195 vencsys clock support
Date: Wed, 25 Aug 2021 19:03:53 +0800	[thread overview]
Message-ID: <CAGXv+5FuLTw9jmXEifkfKKYiN-vur3jBbwZWjL5m8vTkoP6VMA@mail.gmail.com> (raw)
In-Reply-To: <20210820111504.350-20-chun-jie.chen@mediatek.com>

On Fri, Aug 20, 2021 at 7:31 PM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vencsys clock controller which provide clock gate
> control for video encoder.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile          |  2 +-
>  drivers/clk/mediatek/clk-mt8195-venc.c | 69 ++++++++++++++++++++++++++
>  2 files changed, 70 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-venc.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 3c8c8cdbd3ef..82ffcc4f2c52 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -82,6 +82,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \
>                                         clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o \
> -                                       clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o
> +                                       clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o clk-mt8195-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c
> new file mode 100644
> index 000000000000..10702a4ad5ff
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-venc.c
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +static const struct mtk_gate_regs venc_cg_regs = {
> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_VENC(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate venc_clks[] = {
> +       GATE_VENC(CLK_VENC_LARB, "venc_larb", "top_venc", 0),
> +       GATE_VENC(CLK_VENC_VENC, "venc_venc", "top_venc", 4),
> +       GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "top_venc", 8),
> +       GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "top_venc", 12),
> +       GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "top_venc", 16),
> +       GATE_VENC(CLK_VENC_GALS, "venc_gals", "top_venc", 28),
> +};
> +
> +static const struct mtk_gate venc_core1_clks[] = {
> +       GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "top_venc", 0),
> +       GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "top_venc", 4),
> +       GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "top_venc", 8),
> +       GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "top_venc", 12),
> +       GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "top_venc", 16),
> +       GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "top_venc", 28),

The two hardware blocks look the same. Are there any actual differences?
I am somewhat skeptical about using different compatible strings just
to provide different clock names. This is normally handled with
"clock-output-names" properties in the device tree.

ChenYu

> +};
> +
> +static const struct mtk_clk_desc venc_desc = {
> +       .clks = venc_clks,
> +       .num_clks = ARRAY_SIZE(venc_clks),
> +};
> +
> +static const struct mtk_clk_desc venc_core1_desc = {
> +       .clks = venc_core1_clks,
> +       .num_clks = ARRAY_SIZE(venc_core1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_venc[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vencsys",
> +               .data = &venc_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-vencsys_core1",
> +               .data = &venc_core1_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_venc_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-venc",
> +               .of_match_table = of_match_clk_mt8195_venc,
> +       },
> +};
> +builtin_platform_driver(clk_mt8195_venc_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

  reply	other threads:[~2021-08-25 11:04 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-20 11:14 [v2 00/24] Mediatek MT8195 " Chun-Jie Chen
2021-08-20 11:14 ` [v2 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-08-23  6:53   ` Chen-Yu Tsai
2021-08-24 14:44     ` Rob Herring
2021-08-20 11:14 ` [v2 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-08-24 15:17   ` Rob Herring
2021-08-25 11:39   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 03/24] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-08-20 11:14 ` [v2 04/24] clk: mediatek: Add API for clock resource recycle Chun-Jie Chen
2021-08-23  6:40   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 05/24] clk: mediatek: Fix resource leak in mtk_clk_simple_probe Chun-Jie Chen
2021-08-23  6:42   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 06/24] clk: mediatek: Add MT8195 apmixedsys clock support Chun-Jie Chen
2021-08-23  9:21   ` Chen-Yu Tsai
2021-08-23  9:56     ` Chen-Yu Tsai
2021-08-29 18:26   ` Stephen Boyd
2021-08-20 11:14 ` [v2 07/24] clk: mediatek: Add MT8195 topckgen " Chun-Jie Chen
2021-08-23 11:16   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 08/24] clk: mediatek: Add MT8195 peripheral " Chun-Jie Chen
2021-08-23 11:22   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 09/24] clk: mediatek: Add MT8195 infrastructure " Chun-Jie Chen
2021-08-23 11:32   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 10/24] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 11/24] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-08-23 12:13   ` Chen-Yu Tsai
2021-09-10 10:52     ` Chun-Jie Chen
2021-08-20 11:14 ` [v2 12/24] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 13/24] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-08-23 12:20   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 14/24] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-08-23 12:02   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 15/24] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-08-23 12:08   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 16/24] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-08-23 12:21   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 17/24] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-08-25 10:52   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 18/24] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-08-25 10:55   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 19/24] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-08-25 11:03   ` Chen-Yu Tsai [this message]
2021-09-10 11:09     ` Chun-Jie Chen
2021-09-14  3:47       ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 20/24] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-08-25 10:59   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 21/24] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-08-25 11:00   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 22/24] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:34   ` Chen-Yu Tsai
2021-09-10 11:04     ` Chun-Jie Chen
2021-08-20 11:15 ` [v2 23/24] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-08-23 12:50   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 24/24] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-08-23 12:48   ` Chen-Yu Tsai

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