From: Chen-Yu Tsai <wenst@chromium.org>
To: Brian Norris <briannorris@chromium.org>
Cc: "Heiko Stübner" <heiko@sntech.de>,
"Thomas Hebb" <tommyhebb@gmail.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip@lists.infradead.org>,
"Sandy Huang" <hjc@rock-chips.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] drm/rockchip: dsi: Disable PLL clock on bind error
Date: Tue, 28 Sep 2021 12:16:31 +0800 [thread overview]
Message-ID: <CAGXv+5GxCHJM_CewS8dPTLc7NPC6jcKZvrUFat0nemzZpu8PUQ@mail.gmail.com> (raw)
In-Reply-To: <20210927105928.v2.3.I8bb7a91ecc411d56bc155763faa15f289d7fc074@changeid>
On Tue, Sep 28, 2021 at 2:00 AM Brian Norris <briannorris@chromium.org> wrote:
>
> Fix some error handling here noticed in review of other changes.
>
> Reported-by: Chen-Yu Tsai <wenst@chromium.org>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
Fixes: 2d4f7bdafd70 ("drm/rockchip: dsi: migrate to use dw-mipi-dsi
bridge driver")
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Additionally, I would move patch 2 and this patch before the first patch,
as these two fix a commit introduced in v5.0, while the first patch fixes
something introduced in v5.14. This would make automatic backporting cleaner.
> ---
>
> Changes in v2:
> - New
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index fa4080176719..0ed13d81fe60 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -943,7 +943,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
> ret = clk_prepare_enable(dsi->grf_clk);
> if (ret) {
> DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
> - goto out_pm_runtime;
> + goto out_pll_clk;
> }
>
> dw_mipi_dsi_rockchip_config(dsi);
> @@ -955,17 +955,19 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
> ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
> if (ret) {
> DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
> - goto out_pm_runtime;
> + goto out_pll_clk;
> }
>
> ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
> if (ret) {
> DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> - goto out_pm_runtime;
> + goto out_pll_clk;
> }
>
> return 0;
>
> +out_pll_clk:
> + clk_disable_unprepare(dsi->pllref_clk);
> out_pm_runtime:
> pm_runtime_put(dsi->dev);
> if (dsi->slave)
> --
> 2.33.0.685.g46640cef36-goog
>
next prev parent reply other threads:[~2021-09-28 4:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 17:59 [PATCH v2 0/3] Fix Rockchip MIPI DSI display init timeouts Brian Norris
2021-09-27 17:59 ` [PATCH v2 1/3] drm/rockchip: dsi: Hold pm-runtime across bind/unbind Brian Norris
2021-09-27 19:17 ` Tom Hebb
2021-09-27 19:57 ` Brian Norris
2021-09-27 22:53 ` Brian Norris
2021-09-27 17:59 ` [PATCH v2 2/3] drm/rockchip: dsi: Fix unbalanced clock on probe error Brian Norris
2021-09-27 17:59 ` [PATCH v2 3/3] drm/rockchip: dsi: Disable PLL clock on bind error Brian Norris
2021-09-28 4:16 ` Chen-Yu Tsai [this message]
2021-09-28 21:11 ` Brian Norris
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