From: Jack Miller <jack@codezen.org>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc: Jack Miller <jack@codezen.org>, Borislav Petkov <bp@suse.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0
Date: Thu, 29 Jun 2017 11:22:35 -0500 [thread overview]
Message-ID: <CAGXwabQ5-1CVkU4nm+OUYf4rZ-iCfgV54VrPQ9aqvK_JQUDRBw@mail.gmail.com> (raw)
In-Reply-To: <BN6PR1201MB01318E429564EB7A27FE4844F8DD0@BN6PR1201MB0131.namprd12.prod.outlook.com>
On Wed, Jun 28, 2017 at 1:58 PM, Ghannam, Yazen <Yazen.Ghannam@amd.com> wrote:
>> With my patch applied, I see entries like l3_cache under hardware thread 0's
>> directory (it's shifted to CPU 1, so machinecheck1).
>> Without my patch, only machinecheck0 has anything interesting in it
>> (insn_fetch, l2_cache etc.) because the init failed on CPU 1.
>>
>
> What happens with SMT off?
I haven't been able to test with SMT off (since it's apparent that
'nosmt' doesn't really do anything and I don't locally have a firmware
option to turn it off).
First things first though, like Boris I'd like to know if there's a
better way to detect this master thread, other than by APIC ID. Right
now I'm working on a v2 that will remove the CPU check, let each one
perform the rdmsr and only update empty bank info. I believe this call
is being serialized elsewhere (need to check), but if I could keep
this patch to a one-liner by detecting the right thread, I'd like to.
Jack
next prev parent reply other threads:[~2017-06-29 16:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-28 0:06 [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0 Jack Miller
2017-06-28 9:22 ` Borislav Petkov
2017-06-28 17:44 ` Jack Miller
2017-06-28 18:00 ` Ghannam, Yazen
2017-06-28 18:53 ` Jack Miller
2017-06-28 18:58 ` Ghannam, Yazen
2017-06-29 16:22 ` Jack Miller [this message]
2017-06-29 17:58 ` Ghannam, Yazen
2017-06-28 18:16 ` Borislav Petkov
2017-06-28 18:51 ` Ghannam, Yazen
2017-06-28 18:55 ` Borislav Petkov
2017-06-29 18:08 ` [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array Yazen Ghannam
2017-06-30 15:57 ` Jack Miller
2017-07-17 5:19 ` Borislav Petkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAGXwabQ5-1CVkU4nm+OUYf4rZ-iCfgV54VrPQ9aqvK_JQUDRBw@mail.gmail.com \
--to=jack@codezen.org \
--cc=Yazen.Ghannam@amd.com \
--cc=bp@suse.de \
--cc=linux-kernel@vger.kernel.org \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).