From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752580AbdLFQLY (ORCPT ); Wed, 6 Dec 2017 11:11:24 -0500 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:48214 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751604AbdLFQLI (ORCPT ); Wed, 6 Dec 2017 11:11:08 -0500 X-Google-Smtp-Source: AGs4zMYSR6PgBzotk2R4HnRvFEb7Q9L7UcOZAXbxBfTME2NCPkVgw7kkh2vTJxxkozIV9S/Ep0dlIUKb/Pe7Cl9ewcA= MIME-Version: 1.0 In-Reply-To: <20171206155608.tuw73ht6gq7hyrho@flea.lan> References: <20171204051912.7485-1-wens@csie.org> <20171204051912.7485-3-wens@csie.org> <20171205195956.xdil2dsbtfwx35jj@flea.lan> <20171206155608.tuw73ht6gq7hyrho@flea.lan> From: Chen-Yu Tsai Date: Thu, 7 Dec 2017 00:10:39 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/2] clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks To: Maxime Ripard Cc: Chen-Yu Tsai , Michael Turquette , Stephen Boyd , linux-arm-kernel , linux-clk , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 6, 2017 at 11:56 PM, Maxime Ripard wrote: > Hi, > > On Wed, Dec 06, 2017 at 10:30:26AM +0800, Chen-Yu Tsai wrote: >> On Wed, Dec 6, 2017 at 3:59 AM, Maxime Ripard >> wrote: >> > Hi, >> > >> > On Mon, Dec 04, 2017 at 01:19:12PM +0800, Chen-Yu Tsai wrote: >> >> On the A64, the MMC module clocks are fixed in the new timing mode, >> >> i.e. they do not have a bit to select the mode. These clocks have >> >> a 2x divider somewhere between the clock and the MMC module. >> >> >> >> To be consistent with other SoCs supporting the new timing mode, >> >> we model the 2x divider as a fixed post-divider on the MMC module >> >> clocks. >> >> >> >> This patch adds the post-dividers to the MMC clocks. >> >> >> >> Signed-off-by: Chen-Yu Tsai >> > >> > I had a doubt applying that one... sorry. >> > >> >> --- >> >> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 57 +++++++++++++++++++++++------------ >> >> 1 file changed, 37 insertions(+), 20 deletions(-) >> >> >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> >> index 2bb4cabf802f..ee9c12cf3f08 100644 >> >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c >> >> @@ -400,28 +400,45 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, >> >> BIT(31), /* gate */ >> >> 0); >> >> >> >> +/* >> >> + * MMC clocks are the new timing mode (see A83T & H3) variety, but without >> >> + * the mode switch. This means they have a 2x post divider between the clock >> >> + * and the MMC module. This is not documented in the manual, but is taken >> >> + * into consideration when setting the mmc module clocks in the BSP kernel. >> >> + * Without it, MMC performance is degraded. >> >> + * >> >> + * We model it here to be consistent with other SoCs supporting this mode. >> >> + * The alternative would be to add the 2x multiplier when setting the MMC >> >> + * module clock in the MMC driver, just for the A64. >> >> + */ >> >> static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", >> >> "pll-periph1-2x" }; >> >> -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, >> >> - 0, 4, /* M */ >> >> - 16, 2, /* P */ >> >> - 24, 2, /* mux */ >> >> - BIT(31), /* gate */ >> >> - 0); >> >> - >> >> -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, >> >> - 0, 4, /* M */ >> >> - 16, 2, /* P */ >> >> - 24, 2, /* mux */ >> >> - BIT(31), /* gate */ >> >> - 0); >> >> - >> >> -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, >> >> - 0, 4, /* M */ >> >> - 16, 2, /* P */ >> >> - 24, 2, /* mux */ >> >> - BIT(31), /* gate */ >> >> - 0); >> >> +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", >> >> + mmc_default_parents, 0x088, >> >> + 0, 4, /* M */ >> >> + 16, 2, /* P */ >> >> + 24, 2, /* mux */ >> >> + BIT(31), /* gate */ >> >> + 2, /* post-div */ >> >> + 0); >> >> + >> >> +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", >> >> + mmc_default_parents, 0x08c, >> >> + 0, 4, /* M */ >> >> + 16, 2, /* P */ >> >> + 24, 2, /* mux */ >> >> + BIT(31), /* gate */ >> >> + 2, /* post-div */ >> >> + 0); >> >> + >> > >> > Are you sure that the divider there for the non-eMMC clocks? Usually, >> > the new mode is only here for the eMMC, so we would divide the rate by >> > two in the non-eMMC case. >> >> The new mode is there for all MMC controllers. The other two MMC >> controllers even have the old/new timing mode switch. In case you >> forgot we have ".need_new_timings" set for the A64 compatible. > > But then, shouldn't we model them as such, using the work you did on > the A83t clocks? On the A64, the clocks don't have the switch. Only the MMC controller does. On the A83T, both do. ChenYu >> But to eliminate any doubts or concerns, I've rerun tests for the >> micro SD card, instead of the eMMC. And yes the results are the same, >> 2x improvement (12 MB/s vs 23.7 MB/s). > > Ok, good. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com